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TMC2192
10 Bit Encoder
Features
* Multiple input formats - 20 bit CCIR601 - 10 bit CCIR656 - 10 bit Digital Composite * Synchronization modes - Master - Slave - Genlock - CCIR656 * Subcarrier modes - Free-run - Subcarrier reset - Genlock - DRS-lock * Ancillary Data Control (ANC) * Pixel rates from 10 MHz to 15 MHz * Programmable horizontal timing * Programmable vertical blanking interval (VBI) * Line-by-line pedestal enable * Programmable pedestal height from -20 IRE to 20 IRE * Programmable burst amplitude and phase * Controlled edge rates for - Sync - Burst - Active video
* * * * *
* * * * * *
Programmable color space matrix 8:8:8 video reconstruction Three 10 bit D/A's with independent trim Individual power down modes for each D/A Multiple output formats - S-video - Composite - Digital composite output Pin-driven and data-driven, window keying Closed Caption waveform generation (13.5 MHz only) Sin(X)/X compensation filter 5 bit VBI line counter 3 bit field counter Internal test pattern generation - 100% Color Bars - 75% Color Bars - Modulated Ramp
Applications
* Broadcast Television * Nonlinear Video Processing
Block Diagram
PD[23:0] C BYP LUMA
PREPROCESSER
OL[4:0] KEY
OVERLAY MIXER
y cb cr
U Gain Adjustment V Chroma Modulator
INTERP.
LUMA R REF C BYP LUMA LUMA
Y
INTERP.
CHROMA R REF CHROMA COMP
CC
CVBS[9:0]
SYNC INSERT
+
C BYP
KEY MIX
INTERP.
COMPOSITE RREF COMP DAC REF.
FVHGEN
MPU
PDCIN/PDCOUT
HSOUT
VSOUT
LINE[4:0]
FLD[2:0]
VSIN DCVEN\
PXCK
RESET
A[1:0]/SA[1:0]
SERB
D[7:0]
R/W\/SDA
CS/SCL
2194001a
VREF
HSIN
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TMC2192
PRODUCT SPECIFICATION
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Applications. . . . . . . . . . . . . . . . . . . . . . . . .1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . .1 10 Bit Encoder . . . . . . . . . . . . . . . . . . . . . . .1 List of Figures . . . . . . . . . . . . . . . . . . . . . . .3 List of Tables . . . . . . . . . . . . . . . . . . . . . . . .3 Pin Assignments . . . . . . . . . . . . . . . . . . . . .4 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . .4 Functional Description . . . . . . . . . . . . . . . .7
Input Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Color Space Matrix . . . . . . . . . . . . . . . . . . . . . . 9 Synchronization Modes . . . . . . . . . . . . . . . . . 10 Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 10 Blanking Control . . . . . . . . . . . . . . . . . . . . . . . 11 Pixel Data Control . . . . . . . . . . . . . . . . . . . . . . 11 Edge Shaping. . . . . . . . . . . . . . . . . . . . . . . . . . 11 Horizontal Programming. . . . . . . . . . . . . . . . . 12 Vertical Timing . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chrominance Processor . . . . . . . . . . . . . . . . . Subcarrier Programming . . . . . . . . . . . . . . . NTSC Subcarrier . . . . . . . . . . . . . . . . . PAL Subcarrier . . . . . . . . . . . . . . . . . . . PAL-M Subcarrier . . . . . . . . . . . . . . . . . Subcarrier Synchronization. . . . . . . . . . . . . SCH Phase Error Correction. . . . . . . . . . . . Burst Envelope . . . . . . . . . . . . . . . . . . . . . . Color-Difference Low-Pass Filters. . . . . . . . Sync and Pedestal Insertion. . . . . . . . . . . . . . Pedestal Enable . . . . . . . . . . . . . . . . . . . . . Pedestal Height . . . . . . . . . . . . . . . . . . . . . . Sync and Blank Insertion . . . . . . . . . . . . . . Closed Caption Insertion . . . . . . . . . . . . . . . . Line Selection . . . . . . . . . . . . . . . . . . . . . . . Parity Generation . . . . . . . . . . . . . . . . . . . . Operating Sequence . . . . . . . . . . . . . . . . . . 21 21 21 21 21 22 22 23 23 23 23 24 24 24 24 24 24 Interpolation Filters . . . . . . . . . . . . . . . . . . . . . 25 x/Sin(x) Filter . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output Data Formats. . . . . . . . . . . . . . . . . . . . 25 Digital Composite Output . . . . . . . . . . . . . . . . 26 Ancillary Data. . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating Modes. . . . . . . . . . . . . . . . . . . . . 27 Layering Engine. . . . . . . . . . . . . . . . . . . . . . . . 28 Overlay Mixer . . . . . . . . . . . . . . . . . . . . . . . 28 Hardware Keying . . . . . . . . . . . . . . . . . . . . . . . 29 Data Keying . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Parallel Microprocessor Interface . . . . . . . . . 29 Serial Control Port (R-Bus) . . . . . . . . . . . . . . . 31 Data Transfer via Serial Interface . . . . . . . . 31 Serial Interface Read/Write Examples . . . . 31
Control Register Map . . . . . . . . . . . . . . . . 33 Control Register Definitions . . . . . . . . . . 35 Absolute Maximum Ratings . . . . . . . . . . . 60 Operating Conditions . . . . . . . . . . . . . . . . 60 Electrical Characteristics . . . . . . . . . . . . . 62 Switching Characteristics . . . . . . . . . . . . 62 System Performance Characteristics . . . 63 Applications Discussion . . . . . . . . . . . . . 63
Layout Considerations . . . . . . . . . . . . . . . . . . 64 Output Low-Pass Filters . . . . . . . . . . . . . . . . . 67
Mechanical Dimensions . . . . . . . . . . . . . . 71
100-Lead MQFP . . . . . . . . . . . . . . . . . . . . . . . . 71
Ordering Information . . . . . . . . . . . . . . . . 72 Life Support Policy . . . . . . . . . . . . . . . . . . 72
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PRODUCT SPECIFICATION
TMC2192
List of Figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Input Formats . . . . . . . . . . . . . . . . . . . . . .7 24 bit Input Format . . . . . . . . . . . . . . . . . .7 CCIR656 Input Format . . . . . . . . . . . . . . .8 10 bit Input Format . . . . . . . . . . . . . . . . . .8 20 bit 4:2:2 Input Format . . . . . . . . . . . . .8 20 bit 4:4:4 Input Format . . . . . . . . . . . . .8 Propagation Delay through the Encoder . . . . . . . . . . . . . . . . . . . . . . . . .10 Horizontal Timing . . . . . . . . . . . . . . . . . .13 Horizontal Timing - Vertical Blanking . . .13 Horizontal Timing - 1st Half-line. . . . . . .14 Horizontal Timing - 2nd Half-line . . . . . .14 NTSC Vertical Interval . . . . . . . . . . . . . .15 PAL Vertical Interval . . . . . . . . . . . . . . . .17 PAL-M Vertical Interval . . . . . . . . . . . . . .19 Burst Envelope . . . . . . . . . . . . . . . . . . . .23 Gaussian Filter Response . . . . . . . . . . .23 Interpolation Filter. . . . . . . . . . . . . . . . . .25 Interpolation Filter - Passband Detail . . . . . . . . . . . . . . . . . . . . . . . . . . .25 X/SIN(X) Filter . . . . . . . . . . . . . . . . . . . .25 Layering Engine . . . . . . . . . . . . . . . . . . .28 Overlay Outputs . . . . . . . . . . . . . . . . . . .29 Data Keying . . . . . . . . . . . . . . . . . . . . . .29 Microprocessor Parallel Port - Write Timing . . . . . . . . . . . . . . . . . . . . . .30 Microprocessor Parallel Port - Read Timing . . . . . . . . . . . . . . . . . . . . . .30 Serial Port Read/Write Timing . . . . . . . .31 Serial Interface - Typical Byte Transfer. . . . . . . . . . . . . . . . . . . . . . . . . .32 Serial Interface - Chip Address . . . . . . .32 Typical Analog Reconstruction Filter . . .63 Overall Response . . . . . . . . . . . . . . . . . .63 Typical Layout . . . . . . . . . . . . . . . . . . . . .65 ST-163E Layout . . . . . . . . . . . . . . . . . . .66 Pass Band . . . . . . . . . . . . . . . . . . . . . . .67 Stop Band. . . . . . . . . . . . . . . . . . . . . . . .67 2T Pulse . . . . . . . . . . . . . . . . . . . . . . . . .67 Group Delay . . . . . . . . . . . . . . . . . . . . . .67
List of Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. CSM Coefficient Range . . . . . . . . . . . . . 9 Expected Output Values for the CSM with YCBCR Inputs . . . . . . . . . . . . 9 PDC Edge Control . . . . . . . . . . . . . . . . 11 Horizontal Line Equations. . . . . . . . . . . 12 Horizontal Timing Specifications. . . . . . 13 Vertical Interval Timing Specifications . . . . . . . . . . . . . . . . . . . . 14 Default Horizontal Timing Parameters . . . . . . . . . . . . . . . . . . . . . . 15 NTSC Field/Line Sequence and Identification . . . . . . . . . . . . . . . . . . . . . 16 PAL Field/Line Sequence and Identification . . . . . . . . . . . . . . . . . . . . . 18 PAL-M Field/Line Sequence and Identification . . . . . . . . . . . . . . . . . . . . . 20 Standard Subcarrier Parameters . . . . . 22 Line by Line Pedestal Enable . . . . . . . . 23 Closed Caption Line Selection . . . . . . . 24 D/A Outputs . . . . . . . . . . . . . . . . . . . . . 25 Ancillary Data Format . . . . . . . . . . . . . . 26 Ancillary Data Control - Phase . . . . . . 27 Ancillary Data Control Frequency. . . . . 27 Field Identification and Subcarrier Reset Modes . . . . . . . . . . . . . . . . . . . . 27 Layering and Keying Modes . . . . . . . . . 28 Overlay Address Map . . . . . . . . . . . . . . 29 Parallel Port Control . . . . . . . . . . . . . . . 30 Serial Port Addresses. . . . . . . . . . . . . . 31 Control Register Map . . . . . . . . . . . . . . 33
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TMC2192
PRODUCT SPECIFICATION
Pin Assignments
100 1 81 80 Pin 1 2 3 4 5 6 7 8 9 10 11 12 30 31 50 51 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function VDDA COMP CBYPCOMP Pin 31 32 33 34 Function PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 VDD DGND PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Function PD1 PD0 DGND VDD VSIN HSIN DCVEN SER CS\/SCL R/W\/SDA A1/SA1 A0/SA0 D7 D6 D5 D4 D3 D2 D1 D0 DGND VDD PDC HSOUT VSOUT LINE4 LINE3 LINE2 LINE1 LINE0 Pin 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Function FLD2 FLD1 FLD0 CVBS9 CVBS8 CVBS7 CVBS6 CVBS5 CVBS4 CVBS3 CVBS2 CVBS1 CVBS0 RESET PXCK VDD DGND VREF RREFCOMP AGND
AGND CHROMA 35 CBYPCHROM 36 VDDA 37 RREFCHROM 38 AGND 39 LUMA 40 CBYPLUMA 41 VDDA RREFLUMA AGND AGND VDDA VDDA AGND AGND KEY OL4 OL3 OL2 OL1 OL0 DGND PD23 PD22 PD21 PD20 42 43 44 45 46 47 48 49 50
65-6294-14
Pin Definitions
Pin Name DCVEN Pin Number 57 Value TTL Description Digital CVBS Output Enable. When DCVEN is LOW, the Comp2 output prior to the D/A is routed to D7-0, FLD2-1 providing a digital composite output. When DCVEN is HIGH, D7-0 and FLD2-1 operate in their normal mode. Horizontal Sync Input. When operating in slave, Genlock, or DRS-Lock the TMC2192 will start a new horizontal line with each falling edge of HSIN. Hard Key selection. When the control register bit HKEN is set HIGH and the hardware KEY pin is high, the video data considered to be the foreground. is routed to the COMP2 output. This control signal is data aligned so that the pixel that is present on the PD port when KEY signal is latched is at the midpoint of the key transition. When HKEN is LOW, Key is ignored. CLOCK, SYNC, & CONTROL INPUTS (6 pins)
HSIN
56
TTL
KEY
20
TTL
4
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PRODUCT SPECIFICATION
TMC2192
Pin Definitions (continued)
Pin Name PXCK Pin Number 95 Value TTL Description Pixel Clock Input. PXCK is a clock signal that period is twice the sample rate of the pixel data. The operating range is 20 to 30 MHz. The clock is internally divided by 2 to generate the internal pixel clock, PCK. PXCK drives the entire TMC2192 except the asynchronous microprocessor interface. Master Chip Reset. When LOW, All outputs are tri-stated and the internal state machines and control registers are reset. At rising edge of RESET, all outputs are active, the preset values will be loaded into the control registers and the internal states machines start to operate. Vertical Sync Input. When operating in slave, Genlock, or DRS-Lock the TMC2192 will start a new vertical field with each falling edge of VSIN that is coincident with HSIN. Field Identifier. Field Identifier outputs the current field number. For all video standards the field identifier will cycle through the eight counts. Horizontal Sync Output. The alignment of HSOUT to the pixel data port or DCVBS port is controlled by control register TSOUT. Vertical Blanking Interval Line Identifier. LINE identifies the current line number for the first 31 lines. If the line count is greater than 31 then LINE is 11111b. The first line with a vertical serration is considered to be line 0. Pixel Data Control. When PDCDIR = LOW: At a rising edge, The next pixel starts a controlled ramp of the PD data. At a falling edge, the pixel prior is the last PD used in the ramp. The rising edge is determined by the PDCCNT control register, the falling edge of PDC is determined by the horizontal timing registers. When PDCDIR = HIGH: PDCIN is used to override the internal PDC. When HIGH, the internal PDC controls the blank and unblank window. When LOW, the video remains blanked regardless of the internal PDC. All edges have the same ramp control as the internal PDC. VSOUT 75 TTL Vertical Sync Output. The alignment of VSOUT to the pixel data port or DCVBS port is controlled by control register TSOUT. Composite Data Input Overlay Control Component Data Input Luma Chroma Composite D/A with optional keying
RESET
94
TTL
VSIN
55
TTL
SYNC & CONTROL OUTPUTS (11 pins) FLD[2:0] 81-83 TTL
HSOUT
74
TTL
LINE[4:0]
76-80
TTL
PDC
73
TTL
DATA INPUTS (39 pins) CVBS[9:0] OL[4:0] PD[23:0] LUMA CHROMA COMP 84-93 21-25 27-38, 41-52 10 5 2 TTL TTL TTL 1.35Vp-p 1.35Vp-p 1.35Vp-p
ANALOG INTERFACE - Video Out (5 pins)
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TMC2192
PRODUCT SPECIFICATION
Pin Definitions (continued)
Pin Name CBYPLUMA CBYPCHROM CBYPCOMP RREFLUMA Pin Number 11 6 3 13 Value 0.1 F 0.1 F 0.1 F 1210 Ohm Description Reference Bypass Capacitor for LUMA DAC. Connection point for 0.1 F Capacitor. Reference Bypass Capacitor for CHROMA DAC. Connection point for 0.1 F Capacitor. Reference Bypass Capacitor for COMPOSITE DAC. Connection point for 0.1 F Capacitor. Current Setting Resistor. Connection point for external current setting resistor for LUMA DAC. The resistor is connected between RREFLUMA and GND. Output video levels are inversely proportional to the value of RREF2. Current Setting Resistor. Connection point for external current setting resistor for CHROMA DAC. The resistor is connected between RREFCHROM and GND. Output video levels are inversely proportional to the value of RREFCHROM. Current Setting Resistor. Connection point for external current setting resistor for COMPOSITE DAC. The resistor is connected between RREFCOMP and GND. Output video levels are inversely proportional to the value of RREFCOMP. Voltage Reference Input. External voltage reference input, internal voltage reference output, nominally 1.235V. When SER (HIGH), OLUT/control/pointer address. When SER (LOW), SA[1:0] of serial chip address SA[6:0]. ANALOG INTERFACE - Support (9 pins)
RREFCHROM
8
1210 Ohm
RREFCOMP
99
1210 Ohm
VREF
98
1.235 V
MPU INTERFACE (13 pins) A[1:0]/SA[1:0] CS/SCL D[7:0] RW/SDA SER 61, 62 59 63-70 60 58 TTL
TTL/R-BUS When SER (HIGH), microprocessor port clock. When SER (LOW), serial bus clock. TTL Bi-directional Data Bus. TTL/R-BUS When SER (HIGH), read/write control. When SER (LOW), serial bus bi-directional data. TTL Microprocessor Select. When LOW, the serial interface is enabled. When HIGH, the parallel interface is enabled. Analog ground Digital ground Digital positive power supply Analog positive power supply
POWER & GROUND (17 pins) AGND DGND VDD VDDA 4, 9, 14, 15, 18, 19, 100 26, 40, 53, 71, 97 39, 54, 72, 96 1, 7, 12, 16, 17 0.0V 0.0V +5.0V +5.0V
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PRODUCT SPECIFICATION
TMC2192
Functional Description
Input Formats
Control Registers for this section Address 0x05 0x05 0x06 Bit(s) 7 6-4 0 Name D1OFF INMODE TSOUT
Demuxing of multiplexed data streams depends on which synchronization mode the encoder is operating in. For slave and genlock modes the falling edge of HSIN must be LOW prior to the CB data in order to demux the data correctly. For master mode synchronization the falling edge of HSOUT must be LOW prior to the Y data in order to demux the data correctly. Finally, in 656 mode the demuxing of the data stream is determined by the TRS codes, the first sample after the TRS is considered a CB sample of the CB Y CR YI packet. The control register D1OFF controls the formatting of the incoming luminance data at the pixel data port. When D1OFF is HIGH a blanking level of 6410 is subtracted from the luminance and when D1OFF is LOW the incoming the pixel data is passed through. The inversion of the MSB's on the CB and CR components is controlled by the INMODE control register.
The TMC2192 supports YCBCR component sources on the pixel data port. YCBCR input sources are supported in 10 bit 4:2:2, 20 bit 4:2:2, 20 bit 4:4:4, and 24 bit 4:4:4. In the 4:2:2 cases the color difference components are linearly interpolated to 4:4:4 internally.
INMODE 00 01 1x
23 7 9 9 CB YC BC R YC BC R
16 0
15 7 0 0
PD CR
9
8 0
7 7 Y
0 0
1
0
9
Y
2
2192002A
Figure 1. Input Formats
1.
INMODE = 00, PD[7:0] = PD[23:16] = CB, PD[15:8] = CR
n = (SY+BR+BU+CBP+AV)*2 0 128 x = (SY+BR+BU+CBP)*2
PXCK
tS tH
PD[7:0]
Yn-1
Yn
Y0
Yx
Yx+1
Yx+2
PD[23:16]
CBn-1
CBn
CB0
C Bx
CBx+1
CBx+2
PD[15:8]
CRn-1
CRn
tSP
CR0
CRx
CRx+1
CRx+2
HSIN
tDO tDO
HSOUT
(TSOUT = 1) 2192003A
Figure 2. 24 Bit Input Format
2.
INMODE = 01, PD[23:14] = YCBCR running at 27MHz. data value, after the SAV preamble, is treated as a CB data point in the multiplexed CB, Y, CR Y , D1 data stream. Note: Figure 3, pixel numbering, reflects the SMPTE-125M pixel numbering.
The PD port is clocked at twice the pixel rate, with the data organized as CB Y CR Y, with the cosited Y's following the CB's. In its CCIR-656 time base mode, the demuxed CB, Y, and CR data is synchronized to the SAV preamble. The first
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TMC2192
PRODUCT SPECIFICATION
0
128
(SY+BR+BU+CBP)*2
PXCK
tS tH
PD[23:14]
CB718 Y718
CR718
Y719
FF
00 EAV
00
FV1
CB736
Y736
tDO tHS tDO
FF
00 SAV
00
FV0
CB0
Y0
CR0
Y1
CB2
Y2
HSOUT
(TSOUT = 1)
65-6294-04
Figure 3. CCIR656 Input Format
n = (SY+BR+BU+CBP+AV)*2
0
128
x = (SY+BR+BU+CBP)*2
PXCK
tS tH
PD[23:14]
CBn
Yn
CRn
Yn+1
tSP
CB0
Y0
tHP
CBx
Yx
CRx
Yx+1
CBx+2
Yx+2
HSIN
tDO tDO
HSOUT
(TSOUT = 1)
65-6294-05
Figure 4. 10 bit Input Format
3.
INMODE = 11, PD[9:0] = Y, PD[23:14] = CB/CR
n = (SY+BR+BU+CBP+AV)*2 0 128 x = (SY+BR+BU+CBP)*2
PXCK
tS tH
PD[9:0]
Yn
Yn+1
Y0
Y1
Yx
Yx+1
Yx+2
PD[23:14]
CBn
CRn
tSP
CB0
CR0
CBx
CRx
CBx+2
HSIN
tDO tHS
65-6294-06
tDO
HSOUT
(TSOUT = 1)
Figure 5. 20 bit 4:2:2 Input Format
4.
INMODE = 10, PD[9:0] = Y at PCK, PD[23:14] = CB-CR at PXCK
n = (SY+BR+BU+CBP+AV)*2 0 128 x = (SY+BR+BU+CBP)*2
PXCK
tS tH
PD[9:0]
Yn
Yn+1
Y0
tS
Yx
tH
PD[23:14]
CBn
CRn
CBn+1
CRn+1
tSP
CB0
CR0
CBx
CRx
HSIN
tDO tDO
HSOUT
(TSOUT = 1) 65-6294-07
Figure 6. 20 bit 4:4:4 Input Format
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PRODUCT SPECIFICATION
TMC2192
Color Space Matrix
Control Registers for this section Address 0x30 0x33 0x35 0x3A 0x3B 0x3C Bit(s) 7-0 7-0 7-0 7-4 2-0 2-0 Name MCF1L MCF2L MCF3L MCF1M MCF2M MCF3M Matrix configuration: Ycomposite = MCF1 * Yin U = MCF2 * CB V = MCF3 * CR The color space matrix consists of 3 multipliers with independently adjustable coefficients, and a resolution of 0.00049 (1/2048). The amount of gain varies among coefficients, Table 1 summarizes the gain for each coefficient.
Table 1. CSM Coefficient Range Coefficient MCF1 MCF2 MCF3 Gain Range 0 to 2 0 to 1 0 to 1 11 bit coefficient. 11 bit coefficient. processing block and prior to the sync and pedestal insertion. The blank, pedestal, and sync values are given as a reference. Table 4 gives the default coefficients values for the CSM. Comment
To aid in the programming of the color space matrix Table 2 provides a set of default input and output values for 100% color bars. The component values given will be after the pre-
Table 2. Expected Output Values for the CSM with YCBCR Inputs Inputs Color White Yellow Cyan Green Magenta Red Blue Black Blank Pedestal Sync Y 876 776 614 514 362 262 100 0 64 CB 0 -448 151 -297 297 -151 448 0 CR 0 73 448 -375 375 448 -73 0 Y 536 475 376 315 222 160 61 0 240 44 8 5:2 Outputs U 0 -235 79 -156 156 -79 235 0 V 0 54 -332 -278 278 332 -54 0 Y 568 503 407 340 240 173 66 0 256 0 12 7:3 Outputs U 0 -249 84 -165 165 -84 249 0 V 0 57 -351 -294 294 351 -57 0
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TMC2192
PRODUCT SPECIFICATION
Synchronization Modes
Control Registers for this section Address 0x06 0x06 0x06 Bit(s) 5-3 1 0 Name MODE TOUT TSOUT
CCIR656
The TMC2192 derives all synchronization from the embedded TRS (timing reference signals) information. Blanking of selected lines is determined by the v bit of the TRS. However the control registers VBIENx can override and blank the active video portion of VBI lines regardless of the state of the v-bit.
Genlock
The TMC2192 offers a variety of synchronization modes; these are master, slave, genlock, 656 mode, and DRS-Lock. In master mode, the TMC2192 generates its own timing and the synchronization is supplied externally by HSOUT and VSOUT signals. In slave and genlock modes the TMC2192 derives its timing from the input pins HSIN, VSIN. In 656 mode the timing is driven by the synchronization codes embedded into the data stream.
Master
The TMC2192 is driven by the input synchronization pins HSIN and VSIN. When the falling edge of HSIN and VSIN occurs at the same rising edge of PXCK the TMC2192 will start a new field.VSIN can be either a traditional pulse or the MPEG style field toggle. In both cases the TMC2192 will flywheel through fields 2, 4, 6, and 8 synchronizing only to fields 1, 3, 5, and 7. The TMC2192 collects GRS data and resets its subcarrier phase and frequency to the data embedded in the GRS stream. The GRS detection occurs only on the CBVS port.
DRS
The TMC2192 drives the output pins HSOUT and VSOUT to synchronize the incoming video. A new color frame starts at the rising edge of RESET. The encoder always starts at the 1st vertical serration in field 8 and will freerun the field and line sequence. The control register bit SRESET can be used to synchronize the start of the field and line sequence in master mode by resetting the FVHGEN state machine. Output synchronization signal VSOUT can operate in a traditional sync mode or in a MPEG style field toggle mode.
Slave
The TMC2192 is driven by the input synchronization pins HSIN and VSIN. When the falling edge of HSIN and VSIN occurs at the same rising edge of PXCK the TMC2192 will start a new field.VSIN can be either a traditional pulse or the MPEG style field toggle. In both cases the TMC2192 will flywheel through fields 2, 4, 6, and 8 synchronizing only to fields 1, 3, 5, and 7. Subcarrier phase adjustment is determined by the DRS data. The DRS detection can occur on either the CBVS port or the pixel data port.
The TMC2192 is driven by the input synchronization pins HSIN and VSIN. When the falling edge of HSIN and VSIN occurs at the same rising edge of PXCK the TMC2192 will start a new field.VSIN can be either a traditional pulse or the MPEG style field toggle. In both cases the TMC2192 will flywheel through fields 2, 4, 6, and 8 synchronizing only to fields 1, 3, 5, and 7.
Propagation Delay
The propagation delay from the pixel data (PD) input to the D/A output is 64 PXCK's. Figure 8 shows the propagation delay for both master and slave synchronization modes. For CCIR656 data streams, pixel 736 (pixel 0 in Figure 8) is the midpoint of sync and is 32 PXCK's (24 PXCK's in PAL) after the EAV TRS.
n = (SY+BR+BU+CBP+AV)*2
0
63
65
128
PXCK
PD[23:14]
CBn
Yn
CRn
Yn+1
CB0
Y0
HSIN
tDO
HSOUT
(TSOUT = 1)
DACx
(ANALOG)
DCVBS
(D[7:0],FLD[2:1])
tDO
COMP0
COMP1
65-6294-09
Midpoint of the Falling Edge of Sync
Figure 7. Propagation Delay through the Encoder
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PRODUCT SPECIFICATION
TMC2192
Blanking Control
Control Registers for this section Address 0x04 0x06 0x18 0x19 0x1F Bit(s) 1-0 2 4-0 4-0 7-0 Name PDRM PDCDIR VBIENF1 VBIENF2 PDCCNT
Pixel Data Control
The pixel data control has two modes of operation, as an input or as an output. The mode of operation is determined by the PDCDIR control register. When PDC is an input the internally generated PDC is ANDed with the PDC pin. This allows the user to blank any active video regions. When PDC is an output, the internally generated PDC is the output for the PDC pin. The internal PDC control will toggle to a logic HIGH at the pixel specified by PDCNT and toggle to a logic LOW four pixels prior to the end of the active video region. The starting point and ending point of the active video region (VA) are determined by the control registers 10h to 1Fh. When PDC is used as an input, the sloped edge of the active video region will occur on the next four pixels following the toggle point.
The content of VBIENFx[4:0] selects the first line to contain an active video region in each field, all subsequent lines for the remainder of the field are active. To blank an entire field, the user zeroes the VBIENFx[4:0] control register. In CCIR656 slave mode, the user can selectively blank any enabled line by setting its TRS V bit HIGH. For 525-line systems, NTSC line numbering is employed, with the first vertical serration starting on line 4. PAL line numbering is used with 625-line systems, with each field's line 1 being the start of the first vertical serration. Any line(s) enabled by the closed caption control are automatically unblanked for the closed caption waveform, irrespective of the corresponding values of VBIENF. Table 3. PDC Edge Control PDRM[1:0] 00 Slope type at PDC (HIGH)
Edge Shaping
The TMC2192 has three modes of sloped edges on the active video region and are controlled by PDRM control register.
Slope type at PDC (LOW) The following four pixels have the weighting of 1, 7/8, 1/2, and 1/8 for NTSC and 7/8, 5/8, 3/8, and 1/8 for PAL. The fifth pixel s sampled and scaled 1, 7/8, 1/2 and 1/8 over the next four pixels for NTSC and 7/8, 5/8, 3/8, and 1/8 over the next four pixels for PAL. Slope is off, edge control is dictated by the PD stream to active video end
The following four pixels have the weighting of 1/8, 1/2, 7/8 and 1 for NTSC and 1/8, 3/8, 5/8, and 7/8 for PAL. The fifth pixel is sampled and scaled 1/8, 1/2, 7/8 and 1 over the next four pixels for NTSC and 1/8, 3/8, 5/8, and 7/8 over the next four pixels for PAL. Slope is off, edge control is dictated by the PD stream from active video start
01
1x
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TMC2192
PRODUCT SPECIFICATION
Horizontal Programming
Control registers for this section Address 0x06 0x19 0x19 0x19 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2D 0x2D 0x2D Bit(s) 7-6 7 6 5 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-6 5-4 3-2 1-0 FORMAT SHORT T512 HALFEN SY BR BU CBP XBP VA VC VB EL EH SL SH FP XBP (MSB's) VA (MSB's) VB (MSB's) VC (MSB's) Name
Horizontal interval timing is fully programmable and is established by loading the timing registers with the duration of each horizontal element. The duration is expressed in PCK clock cycles. In this way, any pixel clock rate between 10 MHz and 15 MHz can be accommodated, and any desired standard or non-standard horizontal video timing may be produced. Horizontal timing parameters can be calculated as follows: t = N x ( PCK period ) = N x ( 2 x PXCK period ) where N is the value loaded into the appropriate timing register, and PCK is the pixel clock period. When programming horizontal timing, subtract 5 PCK periods from the calculated values of CBP and add 5 PCK periods to the calculated value for VA. The control register HALFEN enables the 1st half line (UBV) on line 283 for NTSC, PAL-M and line 23 for all other PAL standards when it is LOW.
Table 4. Horizontal Line Equations Line Type EE SE SS ES EB UBB, -BB UVV, -VV UVE, -VE UBV Line ID 00 02 03 01 10 0D, 05 0F, 07 0C, 04 0E Line Length Equals EL + EH + EL + EH SL + SH + EL + EH SL + SH + SL + SH EL + EH + SL + SH EL + EH + EL + EH SY + BR + BU + CBP + VA + FP SY + BR + BU + CBP + VA + FP SY + BR + BU + CBP + VC + FP + EL + EH SY + BR + BU + XBP + VB + FP
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PRODUCT SPECIFICATION
TMC2192
SY
BR
BU
CBP
VA
FP
65-6294-10
Figure 8. Horizontal Timing
Table 5. Horizontal Timing Specifications Parameter FP SY BR BU CBP VA H NTSC-M (s) 1.5 4.7 0.6 2.5 1.6 52.6556 63.5556 PAL-I (s) 1.65 4.7 0.9 2.25 2.55 51.95 64.0 PAL-M (s) 1.9 4.95 0.9 2.25 1.8 51.692 63.492
ming, any pixel rate between 10 and 15 Mpps can be accommodated, and any desired standard or non-standard vertical video timing may be produced. Like horizontal timing parameters, vertical timing parameters are calculated as follows: t = N x ( PCK period ) = N x ( 2 x PXCK period ) where N is the value loaded into the appropriate timing register, and PCK is the pixel clock period. The vertical interval comprises several different line types based upon H, the Horizontal line time. H = (2 x SL) + (2 x SH) [Vertical sync pulses] = (2 x EL) + (2 x EH) [Equalization pulses]
Vertical interval timing is also fully programmable, and is established by loading the timing registers with the duration's of each vertical timing element, the duration expressed in PCK clock cycles. In this way as with horizontal program-
H H/2
EL
EH
SL
SH
65-6294-11
Figure 9. Horizontal Timing - Vertical Blanking
The VB and VC control registers are added to produce the half-lines needed in the vertical interval at the beginning and end of some fields. These must properly mate with components of the normal lines.
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13
TMC2192
PRODUCT SPECIFICATION
H/2
SY
BR
BU
XBP
VB
FP
65-6924-12
Figure 10. Horizontal Timing - 1st Half-line
H/2
SY
BR
BU
CBP
VC
FP EL
EH
65-6294-13
Figure 11. Horizontal Timing - 2nd Half-line
Table 6. Vertical Interval Timing Specifications Parameter H EH EL SH SL NTSC-M (s) 63.5556 29.4778 2.3 4.7 27.1 PAL-I (s) 64 29.65 2.35 4.7 27.3 PAL-M (s) 63.492 29.45 2.3 4.65 27.1
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PRODUCT SPECIFICATION
TMC2192
Table 7. Default Horizontal Timing Parameters
Timing Register (hex) Field Rate (Hz) 59.94 59.94 59.94 50.00 50.00 50.00 60.00 60.00 60.00 Horizontal Freq. (KHz) 15.734266 15.734266 15.734266 15.625000 15.625000 15.625000 15.750000 15,750000 15,750000 Pixel Rate (Mpps) 12.27 13.50 14.32 14.75 13.50 15.00 12.50 13.50 14.30 PXCK Freq. (MHz) 24.54 27.00 28.64 29.50 27.00 30.00 25.01 27.00 28.60 SY 20 3A 40 43 45 40 46 3E 44 47 BR 21 07 08 09 0D 0C 0D 0B 0C 0D BU 22 1F 22 24 21 1E 22 1C 1E 20 CBP XBP 23 0F 11 12 21 22 21 13 13 15 24 23 44 54 6D 4D 73 26 26 4C VA 25 8B CB F7 03 BE 11 86 Bf E8 VC 26 05 1E 30 2B 0E 31 FE 12 22 VB 27 77 98 B5 B7 93 BF 8B 99 AC EL 28 1C 1F 21 23 20 23 1D 1F 21 EH2 29 6A 8E A6 B5 90 BD 70 8E A5 SL2 2A 4C 6D 84 93 70 9A 53 6E 84 SH 2B 3A 40 43 45 40 47 3A 3F 42 FP 2C 12 14 15 19 16 19 18 1A 1B Note CBL 2D 65 65 65 75 65 75 61 65 65 2F 52 59 5F 61 59 62 52 57 5D
Standard NTSC sqr. pixel NTSC CCIR-601 NTSC 4x FSC PAL sqr. pixel PAL CCIR-601 PAL 15 Mpps PAL-M sqr.pixel PAL-M CCIR-601 PAL-M 4x FSC
Notes: 1. XBP, VA, VC, and VB are 10 bit values. The 2 MSBs for these four variables are in Timing Register 2D. 2. EH and SL are 9 bit values. A most significant "1" is forced by the TMC2192 since EH and SL must range from 256 to 511. EH and SL may be extended to 767. Only the eight LSBs are stored in Timing Registers 29 and 2A. 3. Every calculated timing parameter has a minimum value of 5 except EH and SL which have minimum values of 256.
Vertical Timing
The vertical timing is controlled by the FORMAT control register, which dictates the field and line sequence.
524
525 1 2 3
FIELDS 1 AND 3 4 5 6 7 8 9 10 *** 19 20
21
22
UVV HSOUT
UVV
EE
EE
EE
SS
SS
SS
EE
EE
EE
UBB
UBB
UBB
UVV
UVV
VSOUT
(TOUT = 1)
VSOUT
(TOUT = 0)
262
263 264 265
FIELDS 2 AND 4 266 267 268 269 270 271 272 273 *** 282
283
284
285
UVV HSOUT
UVE
EE
EE
ES
SS
SS
SE
EE
EE
EB
UBB
UBB
UBV
UVV
UVV
VSOUT
(TOUT = 1)
VSOUT
(TOUT = 0)
65-6294-15
Figure 12. NTSC Vertical Interval
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TMC2192
PRODUCT SPECIFICATION
Table 8. NTSC Field/Line Sequence and Identification Field 1 FIELD ID = x00 Line 4 5 6 7 8 9 10 ... 19 20 21 22 ... 262 263 264 265 ID SS SS SS EE EE EE UBB UBB UBB UBB UVV UVV UVV UVV UVE EE EE LTYPE 03 03 03 00 00 00 0D 0D 0D 0D 0F 0F 0F 0F 0C 00 00 Field 2 FIELD ID = x01 Line 266 267 268 269 270 271 272 273 ... 282 283 284 ... 524 525 1 2 3
EE SE SS ES EB UBB UVV UVE UBV
Field 3 FIELD ID = x10 Line 4 5 6 7 8 9 10 ... 19 20 21 22 ... 262 263 264 265 ID SS SS SS EE EE EE UBB UBB UBB UBB UVV UVV UVV UVV UVE EE EE LTYPE 03 03 03 00 00 00 0D 0D 0D 0D 0F 0F 0F 0F 0C 00 00 01 03 03 02 00 00 10 0D 0D 0D 0E 0F 0F 0F 0F 00 00 00
Field 4 FIELD ID = x11 Line 266 267 268 269 270 271 272 273 ... 282 283 284 ... 524 525 1 2 3 ID ES SS SS SE EE EE EB UBB UBB UBB UBV UVV UVV UVV UVV EE EE EE LTYPE 01 03 03 02 00 00 10 0D 0D 0D 0E 0F 0F 0F. 0F 00 00 00
ID ES SS SS SE EE EE EB UBB UBB UBB UBV UVV UVV UVV UVV EE EE EE
LTYPE
Equalization pulse Half-line vertical sync pulse, half-line equalization pulse Vertical sync pulse Half-line equalization pulse, half-line vertical sync pulse Equalization broad pulse Black burst Active video Half-line video, half-line equalization pulse half-line black, half-line video
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PRODUCT SPECIFICATION
TMC2192
622
623
FIELDS 1 AND 5 ***
23
24
25
26
624
625
1
2
3
4
5
6
7
22
UVV
HSOUT VSOUT
(TOUT = 1)
-VE
EE
EE
SS
SS
SE
EE
EE
-BB
UBB
***
UBB
UBV
UVV
UVV
UVV
VSOUT
(TOUT = 0)
309
310
FIELDS 2 AND 6 311 312 313 314 315 316 317 318 319 320 *** 334 335
336
337
UVV
HSOUT VSOUT
(TOUT = 1)
-VV
EE
EE
ES
SS
SS
EE
EE
EB
UBB
UBB
***
UBB
UBB
UVV
UVV
VSOUT
(TOUT = 0)
622
623
FIELDS 3 AND 7 ***
23
24
25
26
624
625
1
2
3
4
5
6
7
22
-VV
HSOUT VSOUT
(TOUT = 1)
-VE
EE
EE
SS
SS
SE
EE
EE
UBB
UBB
***
UBB
UBV
UVV
UVV
UVV
VSOUT
(TOUT = 0)
309
310
FIELDS 4 AND 8 311 312 313 314 315 316 317 318 319 320 *** 334 335
336
337
UVV
HSOUT VSOUT
(TOUT = 1)
UVV
EE
EE
ES
SS
SS
EE
EE
EB
-BB
UBB
***
UBB
UBB
UVV
UVV
VSOUT
(TOUT = 0)
65-6294-16
Figure 13. PAL Vertical Interval
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TMC2192
PRODUCT SPECIFICATION
Table 9. PAL Field/Line Sequence and Identification Field 1 & 5 FIELD ID = 000, 100 Line 1 2 3 4 5 6 7 ... 22 23 24 25 26 ... 309 310 311 312
EE SE SS ES EB UBB -BB UVV -VV UVE -VE UBV
Field 2 & 6 FIELD ID = 001, 111 Line 313 314 315 316 317 318 319 320 ... 334 335 336 337 ... 622 623 624 625 ID ES SS SS EE EE EB UBB UBB UBB UBB UBB UVV UVV UVV -VV -VE EE EE LTYPE 01 03 03 00 00 10 0D 0D 0D 0D 0D 0F 0F 0F 07 04 00 00
Field 3 & 7 FIELD ID = 010, 110 Line 1 2 3 4 5 6 7 ... 22 23 24 25 26 ... 309 310 311 312 ID SS SS SE EE EE UBB UBB UBB UBB UBV UVV UVV UVV UVV UVV UVV EE EE LTYPE 03 03 02 00 00 0D 0D 0D 0D 0E 0F 0F 0F 0F 0F 0F 00 00
Field 4 & 8 FIELD ID = 011, 111 Line 313 314 315 316 317 318 319 320 ... 334 335 336 337 ... 622 623 624 625 ID ES SS SS EE EE EB -BB UBB UBB UBB UVV UVV UVV UVV UVV -VE EE EE LTYPE 01 03 03 00 00 10 05 0D 0D 0D 0F. 0F 0F 0F 0F 04 00 00
ID SS SS SE EE EE -BB UBB UBB UBB UBV UVV UVV UVV UVV UVV -VV EE EE
LTYPE 03 03 02 00 00 05 0D 0D 0D 0E 0F 0F 0F 0F 0F 07 00 00
Equalization pulse Half-line vertical sync pulse, half-line equalization pulse Vertical sync pulse Half-line equalization pulse, half-line vertical sync pulse Equalization broad pulse Black burst Black burst with color burst suppressed Active video Active video with color burst suppressed Half-line video, half-line equalization pulse Half-line video, half-line equalization pulse, color burst suppressed. half-line black, half-line video
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PRODUCT SPECIFICATION
TMC2192
521
522 523 524 525
FIELDS 1 AND 5 1 2 3 4 5 6 7 8 9 *** 17
18
UVV
UVV
EE
EE
EE
SS
SS
SS
EE
EE
EE
-BB
-BB
UBB
***
UBB
UVV
HSOUT VSOUT
(TOUT = 1)
VSOUT
(TOUT = 0)
259
260 261 262
FIELDS 2 AND 6 263 264 265 266 267 268 269 270 271 *** 279
280
281
UVV
-VE
EE
EE
ES
SS
SS
SE
EE
EE
EB
-BB
UBB
***
UBB
UBV
UVV
HSOUT VSOUT
(TOUT = 1)
VSOUT
(TOUT = 0)
521
522 523 524 525
FIELDS 3 AND 7 1 2 3 4 5 6 7 8 9 *** 17
18
UVV
-VV
EE
EE
EE
SS
SS
SS
EE
EE
EE
-BB
UBB
UBB
***
UBB
UVV
HSOUT VSOUT
(TOUT = 1)
VSOUT
(TOUT = 0)
258
259
260 261 262
FIELDS 4 AND 8 263 264 265 266 267 268 269 270 271 *** 279
280
281
UVV
-VV
-VE
EE
EE
ES
SS
SS
SE
EE
EE
EB
UBB
UBB
***
UBB
UBV
UVV
HSOUT VSOUT
(TOUT = 1)
VSOUT
(TOUT = 0)
65-6294-17
Figure 14. PAL-M Vertical Interval
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19
TMC2192
PRODUCT SPECIFICATION
Table 10. PAL-M Field/Line Sequence and Identification Field 1 & 5 FIELD ID = 000, 100 Line 1 2 3 4 5 6 7 8 9 ... 17 18 ... 259 260 261 262 ID SS SS SS EE EE EE -BB -BB UBB ... UBB UVV ... UVV -VE EE EE LTYPE 03 03 03 00 00 00 05 05 0D ... 0D 0F ... 0F 04 00 00 Field 2 & 6 FIELD ID = 001, 111 Line 263 264 265 266 267 268 269 270 271 ... 279 280 281 ... 521 522 523 524 525
EE SE SS ES EB UBB -BB UVV -VV UVE -VE UBV
Field 3 & 7 FIELD ID = 010, 110 Line 1 2 3 4 5 6 7 8 9 ... 17 18 ... 258 259 260 261 262 ID SS SS SS EE EE EE -BB UBB UBB ... UBB UVV UVV UVV -VV -VE EE EE LTYPE 03 03 03 00 00 00 05 05 0D ... 0D 0F 0F 0F 07 04 00 00
Field 4 & 8 FIELD ID = 011, 111 Line 263 264 265 266 267 268 269 270 271 ... 279 280 281 ... 521 522 523 524 525 ID ES SS SS SE EE EE EB UBB UBB ... UBB UBV UVV ... UVV UVV EE EE EE LTYPE 01 03 03 02 00 00 10 05 1D ... 0D 0E. 0F ... 0F 0F 00 00 00
ID ES SS SS SE EE EE EB -BB UBB ... UBB UBV UVV ... UVV -VV EE EE EE
LTYPE 01 03 03 02 00 00 10 05 1D ... 0D 0E. 0F ... 0F 07 00. 00 00
Equalization pulse Half-line vertical sync pulse, half-line equalization pulse Vertical sync pulse Half-line equalization pulse, half-line vertical sync pulse Equalization broad pulse Black burst Black burst with color burst suppressed Active video Active video with color burst suppressed Half-line video, half-line equalization pulse Half-line video, half-line equalization pulse, color burst suppressed. half-line black, half-line video
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PRODUCT SPECIFICATION
TMC2192
Chrominance Processor
Control registers for this section: Address 0x06 0x06 0x07 0x11 0x18 0x18 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A Bit(s) 7-6 5-3 5 7 6 5 3 7-0 7-0 7-0 7-0 7-4 3-0 7-4 3-0 7-4 3-0 7-4 Name FORMAT MODE DDSRST DRSSEL GLKCTL1 GLKCTL0 GAUSS_BYP FREQL FREQ3 FREQ2 FREQM SYSPHL SYSPHM BURPHL BURPHM BRSTFULL BRST1 BRST2
NTSC Subcarrier
For NTSC encoding, the subcarrier synthesizer frequency has a simple relationship to the pixel clock period, repeating over 2 lines: The decimal value for the subcarrier phase step is: 455 2 32 FREQx = -------------------------- x 2 pixels line Where the number of pixels/line is: PXCK Frequency pixels line = -----------------------------------------H Period This value must be converted to binary and split into four 8 bit registers, FREQM, FREQ2, FREQ3, and FREQL.
PAL Subcarrier
The PAL relationship is more complex, repeating only once in 8 fields (the well-known 25 Hz offset): ( 1135 4 ) + ( 1 625 ) 32 FREQx = -------------------------------------------------- x 2 pixels line This value must be converted to binary and split as described previously for NTSC. The number of pixels/line is found as in NTSC.
PAL-M Subcarrier
Subcarrier Programming
909 4 32 FREQ = -------------------------- x 2 pixels line SYSPHx establishes the appropriate phase relationship between the internal synthesizer and the chroma modulator. The nominal value for SYSPHx is zero. Other values for SYSPHx must be converted to binary and split into two 8 bit registers, SYSPHM and SYSPHL. Burst Phase (BURPHx) sets up the correct relative NTSC modulation angle. The value for BURPH is: BURPHx = SYSPHx This value must be converted to binary and split into two 8 bit registers, BURPHM and BURPHL.
The color subcarrier is produced by an internal 32 bit digital frequency synthesizer which is completely programmable in frequency and phase. Separate registers, FREQx, SYSPHx, BSTPHx, are provided for phase adjustment of the color burst and of the active video, permitting external delay compensation, color adjustment, etc. FREQx is the subcarrier phase step per pixel and SYSPHx is phase offset at field 1, line 1 (line 4 for NTSC), pixel 1.
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TMC2192
PRODUCT SPECIFICATION
Table 11. Standard Subcarrier Parameters
Subcarrier Register (hex) Field Rate (Hz) 59.94 59.94 59.94 50.00 50.00 50.00 60.00 60.00 60.00 Horizontal Freq. (kHz) 15.734266 15.734266 15.734266 15.625000 15.625000 15.625000 15.750000 15,750000 15,750000 Pixel Rate (Mpps) 12.27 13.50 14.32 14.75 13.50 15.00 12.50 13.50 14.30 PXCK Freq. (MHz) 24.54 27.00 28.64 29.50 27.00 30.00 25.01 27.00 28.60 Subcarrier Freq. (MHz) 3.57954500 3.57954500 3.57954500 4.43361875 4.43361875 4.43361875 3.57561149 3.57561149 3.57561149 BURPHM BURPHL SYSPHM 47 00 00 00 00 00 00 00 00 00 46 00 00 00 00 00 00 00 00 00 45 00 00 00 00 00 00 00 00 00 SYSPHL FREQM 44 00 00 00 00 00 00 00 00 00 43 4A 43 40 4C 54 4B 49 43 40 FREQ2 FREQ3 FREQL 42 AA E0 00 F3 13 AA 45 DF 10 41 AA F8 00 18 15 C6 00 3F 66 40 AB 3E 00 19 96 A1 51 D7 F5
Standard NTSC sqr. pixel NTSC CCIR-601 NTSC 4x FSC PAL sqr. pixel PAL CCIR-601 PAL 15 Mpps PAL-M sqr.pixel PAL-M CCIR-601 PAL-M 4x FSC
Subcarrier Synchronization
There are 5 modes of subcarrier synchronization in the TMC2192, freerun, subcarrier reset, Genlock, DRS-lock and Ancillary Data Control (ANC). * Freerun
At the rising edge of RESET the DDS starts to generate the subcarrier reference and will continue to freerun the subcarrier. When setting the control register DDSRST is HIGH, the TMC2192 will reset the DDS to the SYSPH value on the next field 1, line 1 (line 4 for NTSC), pixel 1 occurrence and will reset this bit to be LOW. This allows the encoder to start with the correct SCH relationship. The phase of the subcarrier reference will drift over time since a 32 bit accumulator has a error of 0.5 Hz when generating the subcarrier reference for NTSC 13.5 MHz. * Subcarrier Reset
the TMC22x5y. The TMC22x5y produces a decoder reference signal (DRS) which contains field identification, PALODD status, relative phase and relative frequency of the composite or S-video input. The DRS is sampled on either the CVBS bus or the PD port, depending on DRSSEL, 60 PXCK's after the falling edge of HSIN. The phase and frequency values are used to update the DDS on a line to line basis, thus synchronizing the subcarrier to an external composite reference. * Ancillary Data Control (ANC)
Subcarrier synchronization in ANC mode is covered in the Ancillary Data Control section of this data sheet.
SCH Phase Error Correction
At the rising edge of RESET the DDS starts to generate the subcarrier reference and will reset the DDS to the SYSPH value every field 1, line 1 (line 4 for NTSC), pixel 1 occurrence. This enables the encoder to maintain the proper SCH relationship. * Genlock
SCH refers to the timing relationship between the 50% point of the leading edge of horizontal sync and the positive or negative zero-crossing of the color burst subcarrier reference. SCH error is usually expressed in degrees of subcarrier phase. In PAL, SCH is defined for line 1 of field 1, but since there is no color burst on line 1, SCH is usually measured at line 7 of field 1. The need to specify SCH relative to a particular line in PAL is due to the 25 Hz offset of PAL subcarrier frequency. Since NTSC has no such 25 Hz offset, SCH applies to all lines. The SCH relationship is important in the TMC2192 when two video sources are being combined or if the composite video output is externally combined with another video source. In these cases, improper SCH phasing will result in a noticeable horizontal jump of one image with respect to another and/or a change in hue proportional to the SCH error between the two sources. SCH phasing can be adjusted by modifying BURPH and SYSPH values by equal amounts. SCH is advanced/delayed by one degree by increasing/decreasing the value of BURPH and SYSPH by approximately B6h. An SCH error of 15o is corrected with SYSPH and BURPH offsets of AAAh.
The Genlock mode allows the TMC2192 to lock to a composite reference when used in conjunction with the TMC22071A Genlocking Video Digitizer. The TMC22071A produces a genlock reference signal (GRS) which contains field identification, PALODD status, relative phase and relative frequency of the composite reference. The GRS is sampled on the CVBS bus 60 PXCK's after the falling edge of HSIN. The phase and frequency values are used to update the DDS on a line to line basis, thus synchronizing the subcarrier to an external composite reference. * DRS-Lock
The DRS-Lock mode allows the TMC2192 to lock its composite output to the decoded composite or S-video input of
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PRODUCT SPECIFICATION
TMC2192
Burst Envelope
The TMC2192 includes the ability to adjust the burst amplitude and the shape of the burst. The Control Registers BRSTFULL, BRST1 and BRST2 hold the magnitude of the burst vector. BRSTFULL is the maximum amplitude of the burst vector. BRST1 and BRST2 determine the intermediate values of the burst vector for the burst envelope shaping. A 5 pixel burst envelope shaping occurs at the rising and falling edges of burst. At the rising edge of burst the next 5 pixels have the following weighting; BRSTFULL - BRST1, BRSTFULL - BRST2, BRSTFULL/2, BRST2, and BRST1. At the falling edge of burst the next 5 pixels have the following weighting; BRST1, BRST2, BRSTFULL/2, BRSTFULL - BRST2, and BRSTFULL - BRST1. With this flexibility the user determine the shape, amplitude and width of the burst signal.
BRSTFULL BRST1 BRST2 BRSTFULL/2 BRSTFULL - BRST2 BRSTFULL - BRST1 BLANK
0 -10 Attenuation (db) -20 -30 -40 -50
65-6294-19
-60 -70 -80 0 0.1 0.2 0.3 0.4 Normalized Frequency (Pixel rate)
0.5
Figure 16. Gaussian Filter Response
Sync and Pedestal Insertion
Control Registers for this section Address 0x06 0x11 0x14 0x15 0x16
65-6294-18
Bit(s) 7-6 5 7-0 7-0 7-0 7-0 6-0 3
Name MODE COMP2DB VBIPEDEM VBIPEDEL VBIPEDOM VBIPENOL PEDHGT1 C2DB_OFF
BU
0x17 0x1A 0x3F
Figure 15. Burst Envelope
Color-Difference Low-Pass Filters
The chrominance portion of a composite video signal must be sufficiently bandlimited to avoid cross-color and crossluminance distortion, and to preclude exceeding the allowable bandwidth of a video channel. The color-difference low-pass filters on the TMC2192 establish chrominance bandwidths which meet the specifications outlined in CCIR Report 624-3, Table II, Item 2.6, for system I over a range of pixel rates from 12.27 Mpps to 14.75 Mpps. Equal bandwidth is established for both colordifference channels.
Pedestal Enable
The TMC2192 has the ability to independently select lines for pedestal insertion during the vertical blanking interval (VBI). For 525-line systems and using the NTSC line numbering convention, in which the first vertical serration is on line 4 for field 1 and line 266 for field 2, the vertical interval lines map to the control registers VBIPEDxy as shown in Table 15.
Table 12. Line by Line Pedestal Enable Bit VBIPEDEL VBIPEDEM VBIPEDOL VBIPEDOM 7 17 25* 279 287* 6 16 24 278 286 5 15 23 277 285 4 14 22 276 284 3 13 21 275 283 2 12 20 274 282 1 11 19 273 281 280 0 10 18
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23
TMC2192
PRODUCT SPECIFICATION
Enabling the pedestal on line 25 enables it for the remainder of field 1, to line 262. Likewise, enabling the pedestal on line 288 enables it for the remainder of field 2.
Pedestal Height
Line Selection
The line to contain CC data is selected by a combination of the CCFLD bit and the CCLINE bits. CCLINE is added to the offset shown in Table 16 to specify the line. Table 13. Closed Caption Line Selection Standard 525 625 Offset 12 274 16 328
Parity Generation
PEDHGT1 determines the height of the pedestal for the luminance channel on the composite path. The range of the pedestal height is from -22.1 to 21.74 IRE in .345 IRE increments.
Sync and Blank Insertion
Field ODD EVEN ODD EVEN
Lines 12-27 274-289 16-31 328-343
The composite paths blank and sync D/A codes are determined by the FORMAT control register. For NTSC and PAL-M formats the blank D/A code is 240 (295 mV) and the sync D/A code is 8 (9 mV). For all other PAL formats the blank D/A code is 256 (314 mV) and the sync D/A code is 12 (14 mV). In all cases the sync edges are sloped to insure the proper rise and fall times in all video standards.
Closed Caption Insertion
Control Registers for this section
Standard Closed-Caption signals employ ODD parity, which may be automatically generated by setting CCPAR HIGH. Alternatively, parity may be generated externally as part of the bytes to be transmitted, and, with CCPAR LOW, the entire 16 bits loaded into the CCDx registers will be sent unchanged.
Operating Sequence
Address 0x1C 0x1D 0x1E 0x1E 0x1E 0x1E 0x1E
Bit(s) 7-6 1-0 7 6 5 4 3-0
Name CCD1 CCD2 CCON CCRTS CCPAR CCFLD CCLINE
A typical operational sequence for closed-caption insertion on line xx is: Read Register 1E and check that bit 7 is LOW, indicating that the CCDx registers are ready to accept data. If ready, write two bytes of CC data into registers 1C and 1D. Write into register 1E the proper combination of CCFLD and CCLINE. CCPAR may be written as desired. Set CCRTS HIGH. The CC data is transmitted during the specified line.
The TMC2192 includes a flexible closed-caption processor. It may be programmed to insert a closed caption signal on any line within a range of 16 lines on ODD and/or EVEN fields. Closed Caption insertion overrides all other configurations of the encoder: if it is specified on an active video line, it takes precedence over the video data and removes NTSC setup if setup has been programmed for the active video lines. Closed Caption is only available when the TMC2192 is in a 13.5 MHz pixel rate. Closed caption is turned on by setting CCON HIGH. Whenever the encoder begins producing a line specified by CCFLD and CCLINE, it will insert a closed caption line in its place. If CCRTS is HIGH, the data contained in CCDx will be sent. IF CCRTS is LOW, Null bytes (hex 00 with ODD parity) will be sent.
As soon as CCDx s transferred into the CC processor (and CCRTS goes LOW), new data may be loaded into registers 1C and 1D. This allows the user to transmit CC data on several consecutive lines by loading data for line n+1 while data is being sent on line n.
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PRODUCT SPECIFICATION
TMC2192
Interpolation Filters
Each video output on the TMC2192 is digitally filtered with sharp-cutoff low-pass interpolation filters. These filters ensure that the frequency band above base-band video and below the pixel frequency (fS/4 to 3fS/4, where fS is the PXCK frequency) are sufficiently suppressed. Since these are fixed-coefficient digital filters, their filter characteristics depend upon clock rate.
10 0 -10 Attenuation (db) -20 -30 -40 -50 -60 -70 -80 0 0.2 0.4 0.6 0.8 1 Frequency (Pixel rate)
65-6294-21
x/Sin(x) Filter
Control Registers for this section Address 0x11 Bit(s) 4 Name SINEN
The TMC2192 contains a selectable X/sin(X) filter prior to each DAC. The X/sin(X) filter boosts the high frequency data to negate the sin(X)/X roll-off associated with D/A converters.
1.5 1 Attenuation (db) 0.5 0 -0.5
65-6294-22
X/Sin(x) Filter Compensated D/A Output
-1 -1.5 -2 0 0.1
Sin(x)/x D/A Roll-Off
Figure 17. Interpolation Filter
0.2
0.3
0.4
0.5
Normalized Frequency (PXCK)
Figure 19. X/SIN(X) Filter
0.5 0 Attenuation (db) -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 0 0.1 0.2 0.3 0.4 Frequency (Pixel rate)
65-6294-20
Output Data Formats
Control Registers for this section Address 0x10 0x10 0x10 0x3F 0x3F Bit(s) 5 6 7 7 4 Name LUMADIS CHROMADIS COMPDIS SEL_CLK SEL_PIX
0.5
Figure 18. Interpolation Filter - Passband Detail
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25
TMC2192
PRODUCT SPECIFICATION
Analog outputs of the TMC2192 are driven by three 10 bit D/A converters, operating at twice the pixel rate. The outputs drive standard video levels into 37.5 or 75 Ohm loads. An internal voltage reference is used to provide reference current for the D/A converters. For more accurate levels, an external fixed or variable voltage reference source is accommodated. The video signal levels from the TMC2192 may be adjusted by varying the common Vref or the 3 independent Rrefs. Each video D/A converter has an independent reference resistor that can adjust the output gain. D/A Matching is achieved by trimming the each external reference resistor of each D/A.
Ancillary Data
Control Registers for this section Address 0x07 0x07 0x07 0x08 Bit(s) 2 1 0 7-0 Name ANCFREN ANCPHEN ANCTREN ANCID
Digital Composite Output
In addition, the TMC2192 supplies a 10 bit digital composite signal on pins D[7:0] and FLD[2:1]. The digital composite output can be either an interpolated signal on a non-interpolated signal, this controlled by the control register SEL_CLK. Table 14. Ancillary Data Format Word ID ANC2 ANC1 ANC0 TT MM LL FIELD PH1 PH0 FR4 FR3 FR2 FR1 FR0
Note: 1. P = odd parity bit, x = reserved bit will be ignored
The TMC2192 is designed to accept 15 words of ancillary data after the active video pixels at the end of each horizontal line. Ancillary data may occur once per line, once per field, once per eight fields, on random lines, or not al all. The TMC2192 does not assume ancillary data is present on a regular basis.
Description Ancillary Data Header (Timing Reference Signal)
B7 0 1 1 TT6 0 0 x x PHV PH6 FRV FR27 FR20 FR13 FR6
B6 0 1 1 TT5 D11 D5 x x PH12 PH5 x FR26 FR19 FR12 FR5
B5 0 1 1 TT4 D10 D4 x x PH11 PH4 x FR25 FR18 FR11 FR4
B4 0 1 1 TT3 D9 D3 SVF x PH10 PH3 FR31 FR24 FR17 FR10 FR3
B3 0 1 1 TT2 D8 D2 F2 x PH9 PH2 FR30 FR23 FR16 FR9 FR2
B2 0 1 1 TT1 D7 D1 F1 x PH8 PH1 FR29 FR22 FR15 FR8 FR1
B1 0 1 1 TT0 D6 D0 F0 x PH7 PH0 FR28 FR21 FR14 FR7 FR0
B0 0 1 1 P P P P P P P P P P P P
Data Type Word Count Field ID/Synchronous Video Flag reserved Subcarrier Phase Subcarrier Frequency
The first three words of ancillary data comprise the TRS signal (ANC2-0) which indicates the end of active video. Also known as the Ancillary data header, the TRS signal is a 00h, FFh, FFh sequence. Except for the TRS words, ancillary data bit 0 (B0, LSB) is odd parity for B7-1. The data type word (TT) is used to specify the ancillary data type. The TMC2192 compares this 7 bit value with the contents of the ANCID control register. If there is a match, the ancillary data will be processed. If there is no match, the TMC2192 ignores ancillary data.
The word count data (D11-0 in MM, LL) in the ancillary data packet indicate the number of words in ancillary data. Ancillary phase data is used to program the MSBs of the PHASE register. ANCPHEN and PHV determine how ancillary phase data is used. When ancillary data is not present, the TMC2192 assumes PHV = LOW.
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PRODUCT SPECIFICATION
TMC2192
Table 15. Ancillary Data Control - Phase ANCPHEN 0 1 1 PHV x 0 1 Description Ignore ancillary phase data, set PHASE = 0 Ignore ancillary phase data, no change to PHASE Load ancillary phase data into PHASE registers
ancillary frequency data is used. When ancillary data is not present, the TMC2192 assumes FRV = LOW. Table 16. Ancillary Data Control Frequency ANCFREN 0 1 1 FRV x 0 1 Description Ignore ancillary frequency data Ignore ancillary frequency data Load ancillary frequency data into FREQ3-0 registers
Ancillary frequency data is used to program the 32 bits of the FREQ3-0 registers. ANCFREN and FRV determine how
Table 17. Field Identification and Subcarrier Reset Modes ANCTREN Basic Mode 0 0 Genlocking Mode 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 x x 0 0 0 0 1 1 1 1 x x 0 0 1 1 0 0 1 1 x x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Odd field, subcarrier free run Even field Field 1, reset subcarrier at field 1 Field 2 Field 3 Field 4 Field 5 Field 6 Field 7 Field 8 x x x x x x x x 0 1 Odd field, reset subcarrier every 8 fields Even field SVF F2 F1 F0 F (EAV) Field ID / Subcarrier Reset Mode
Field Sequence Mode
Note: 1. The F bit is part of the EAV timing reference code and tracks the F0 bit. Operating Modes
The field number bits (F2-0) from the ancillary data packet FIELD word, are used to program the encoder's field counter depending upon the state of the synchronous video flag (SVF) and the ANCTREN bit in the control register. In the basic operating mode (ANCTREN = LOW), all timing is found in the F bit of EAV. F2-0 and SVF are ignored and the encoder subcarrier synthesizer is reset to the PHASE value every eight fields (when the field counter transitions from 111 (field 8) to 000 (field 1). In the basic mode, ANCFREN and ANCPHEN are typically set LOW, ignoring ancillary frequency and phase data. If ANCFREN and ANCPHEN are HIGH, the TMC2192 uses the incoming ancillary frequency and phase data on a lineby-line basis.
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In genlocking mode (ANCTREN and SVF = HIGH), the subcarrier synthesizer is allowed to free run, with phase and frequency being set from the ancillary data packet PH12-0 and FR31-0 data. The field counter increments just like it does in basic mode. Field sequence mode (ANCTREN = HIGH and SVF = LOW), is the same as basic mode except that the field counter is set by the F2-0 bits in the FIELD word of ancillary data. If ancillary data is not present on a line, the field counter will continue to count as it does in basic mode. When ancillary data is present, the contents of the field counter are loaded with field data (F2-0). In this way, the TMC2192 may be synchronized with an external source by sending field data only once.
27
TMC2192
PRODUCT SPECIFICATION
Layering Engine
Control Registers for this section Address 0x04 0x05 0x07 0x09 0x09 0x09 0x09 0x09 0x09 0x09 Bit(s) 2 3-2 6 7 6 5 4 3 2 1-0 Name SKEN OMIX SKFLIP HKEN BUKEN SKEXT DKDIS EKDIS FKDIS LAYMODE
Address 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
Bit(s) 7-0 7-0 7-0 7-0 7-0 7-0
Name DKEYMAX DKEYMIN EKEYMAX EKEYMIN FKEYMAX FKEYMIN
The TMC2192 features a robust layering engine with three possible input layers controlled by two keying controls. The layer assignments are shown in Table 22, along with the keying control. The keying controls, KEY pin or OL4-0 are aligned with the incoming pixel data stream and are then delayed throughout the chip to be continuously aligned with the input video streams. A generic overview of the keying and layering features is shown in Figure 21.
Table 18. Layering and Keying Modes LAYMODE 0 1 2 3
OL4-0
BACKGROUND Image Source PD PD CVBS CVBS
MIDGROUND Image Source OVERLAY CVBS OVERLAY PD Keying Control OL4-0 KEY or Data Key OL4-0 KEY or Data Key
FOREGROUND Image Source CVBS OVERLAY PD OVERLAY Keying Control KEY or Data Key OL4-0 KEY or Data Key OL4-0
dT PD OVERLAY MIXER YC
PD LOGIC DATA KEY
LOGIC
KEY
dT
dT
OLUT 1/2AMP CVBS dT dT
dT dT
KEYING MIXER
COMP
65-6294-23
Figure 20. Layering Engine
Overlay Mixer
The OL[4:0] bus provides the ability to overlay 30 different 24 bit values onto the pixel data path. The 24 bit overlay colors must be the same format as the incoming Pixel data. For Y,Cb,Cr input formats the range of Y values spans the entire range of the format, 1 to 254, this enables super whites and super blacks in the overlay palette. When OL[4:0] is equal to 00h the pixel data port to be the output of the overlay mixer. If OL[4:0] is in the range of 1 to 31 then the output source is one of 30 possible overlay col-
ors, see Table 22. Overlay Address Map. When OL4-0 equal to 16, the overlay mixer produces a pixel data output with half the luminance magnitude and chrominance magnitude. Any OL4-0 value greater than 16 will result in a overlay mix with a full amplitude overlay and the pixel data with half amplitude pixel data (PD) or half amplitude CVBS data as its values. This allows for transparent overlays or produce shadow boxes around overlaid text. The midpoint of the rising and falling edges on the mixed output is determined by the transition of the OL[4:0] pins in
28
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PRODUCT SPECIFICATION
TMC2192
relation to the PD port. Control register OMIX chooses among the following set of coefficients; either 0 1/8 1/2 7/8 1, 0 1/2 1 , or 0 1 to switch between the PD port and the over-
lay color. The timing diagram in Figure 22 identifies the three possible output formats that the mixer can produce.
PDx OL[4:0] MixOUT (OMIX = 3) MixOUT (OMIX = 2) MixOUT (OMIX = 1)
A A
B
C
D
E >0
F
G
H
I 0
A A A
7/8B, 1/8OL 1/2C, 1/2OL 1/8D, 7/8OL
OL OL OL
1/8F, 7/8OL 1/2G, 1/2OL 7/8H, 1/8OL
I I I
65-6294-24
B B
1/2C, 1/2OL
OL OL
OL OL
1/2G, 1/2OL
H H
OL
OL
Figure 21. Overlay Outputs
Table 19. Overlay Address Map OL4-0 0 1-15 16 17-31 Result Pixel data is passed through overlay mixer. Overlay is mixed with PD or CVBS at the transitions. Half amplitude PD or half amplitude CVBS is the output of COMP2. Overlay is mixed with half amplitude PD or half amplitude CVBS at the transitions. key value and a minimum key value. If the pixel data is greater than xKEYMIN and less than or equal to xKEYMAX, then a key match is signaled for that channel.
Hardware Keying
The KEY input switches the input to the Comp data path between the composite video generated from the PD port and the CVBS data bus on a pixel-by-pixel basis. This is a "soft" switch is executed over 3 PCK periods to minimize out-ofband transients. Keying is accomplished in the digital composite video domain. The coefficients for the mix are 0, 1/8, 1/2, 7/8, and 1 . The COMP output is the final output for all overlay functions. Hardware keying is enabled by the key Control Register HKEN. Normally, keying is only effective during the active video portion of the encoded video line (as determined by Control Register VA). That is, the horizontal blanking interval is generated by the encoder even if the KEY signal is held HIGH through horizontal blanking. However, it is possible to allow digital horizontal blanking to be passed through from the CVBS bus to the COMP output by setting key Control Register BUKEN HIGH. In this mode, KEY is always active, and may be exercised at will. The KEY input is registered into the encoder just as Pixel data is clocked into the PD port. It is internally pipelined, so the midpoint of the KEY transition occurs at the output of the pixel that was input at the same time at the KEY signal.
xKEYMAX
A B
A<=B KEY MATCH
xKEYMIN xCHANNEL A B A<=B
65-6294-25
Figure 22. Data Keying
By allowing a window of possible key values on each channel the TMC2192 opens a key cube in the color space.
Parallel Microprocessor Interface
The parallel microprocessor interface is active when SER is HIGH and employs a 12-line interface; an 8 bit data bus and 2 bit address location, 1 bit read/write select, and a chip select controlling the timing. Two addresses are required for device programming, one to the pointer and one to the data location. When writing, the address is presented along with a LOW on the R/W pin during the falling edge of CS. Eight bits of data are presented on D7-0 during the subsequent rising edge of CS.
Data Keying
Data keying for each channel Y, Cb, and Cr, is separately enabled or disabled by the control registers DKEYDIS, EKEYDIS, and FKEYDIS. On each channel the eight (8) MSBs of the pixel data are compared against a maximum
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29
TMC2192
PRODUCT SPECIFICATION
In read mode, the address is accompanied by a HIGH on the R/W pin during a falling edge of CS. The data output pins go to a low-impedance state tDOZ after CS falls. Valid data are present on D7-0 tDOM after the falling edge of CS. Because this port operates asynchronously with the pixel timing, there is an uncertainty in this data valid output delay of one PXCK period. This uncertainty does not apply to tDOZ. Writing data to specific control registers of the TMC2192 requires that the 8 bit address of the control register of interest be written prior to the data. This control register address is the base address for subsequent write operations. The base address auto increments by one for each byte of data written after the data byte intended for the base address. If more bytes are transferred than there are available addresses, the address will not increment and remain at its maximum value of 4Ch. Writing data to specific OLUT location of the TMC2192 requires that the 8 bit address of the OLUT location of interest be written prior to the data sequence. This OLUT location address is the base address for subsequent write operations. The base address auto increments by one for each sequence of three (3) bytes of data written after the data byte intended for the base address. The sequence of data
tPWLCS CS tSA R/W tHA
transfer is Y, Cb, Cr , after the Cr byte is transferred the base address will increment by one (1). Table 20. Parallel Port Control A1-0 00 00 01 01 10 10 11 11 R/W 0 1 0 1 0 1 0 1 Action Load D7-0 into Control Register pointer (block 0) Read Control Register pointer on D7-0 Load D7-0 into addressed OLUT Location pointer (block 0) Read addressed OLUT Location pointer on D7-0. Write D7-0 to addressed Control Register Read addressed Control Register on D7-0 Write D7-0 to addressed OLUT Location Read addressed OLUT Location on D7-0
tPWHCS
ADR tSD D7-0
65-6294-26
tHD
Figure 23. Microprocessor Parallel Port - Write Timing
tPWLCS CS tSA R/W tHA tPWHCS
ADR tDOM D7-0 tDOZ
65-6294-27
tHOM
Figure 24. Microprocessor Parallel Port - Read Timing
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PRODUCT SPECIFICATION
TMC2192
Serial Control Port (R-Bus)
In addition to the 12-wire parallel port, a 2-wire serial control interface is provided, active when SER is LOW. Either port alone can control the entire chip. Up to four TMC2192 devices may be connected to the 2-wire serial interface with each device having a unique address. The 2-wire interface comprises a clock (SCL) and a bi-directional data (SDA) pin. The encoder acts as a slave for receiving and transmitting data over the serial interface. When the serial interface is not active, the logic levels on SCL and SDA need to be pulled HIGH by external pull-up resistors. Data received or transmitted on the SDA line must be stable for the duration of the positive-going SCL pulse. Data on SDA must change only when SCL is LOW. If SDA changes state while SCL is HIGH, the serial interface interprets that action as a start or stop sequence. There are six components to serial bus operation: * * * * * * Start signal Slave address byte Block Pointer Offset Pointer Data byte to read or write Stop signal
bit indicates the direction of data transfer, read from or write to the slave device. If the transmitted slave address matches the address of the device (set by the state of the SA1-0 input pins in Table 24), the TMC2192 acknowledges by bringing SDA LOW on the 9th SCL pulse. If the addresses do not match, the TMC2192 will not acknowledge. Table 21. Serial Port Addresses A6 1 1 1 1 A5 0 0 0 0 A4 1 1 1 1 A3 0 0 0 0 A2 1 1 1 1 A1 A0 (SA1) (SA0) 0 0 1 1 0 1 0 1
Data Transfer via Serial Interface
For each byte of data read or written, the MSB is the first bit of the sequence. If the TMC2192 does not acknowledge the master device during a write sequence, the SDA remains HIGH so the master can generate a stop signal. If the master device does not acknowledge the TMC2192 during a read sequence, the encoder interprets this as "end of data". Writing data to specific control registers of the TMC2192 requires that the 8 bit address of the control register of interest be written after the slave address has been established. This control register address is the base address for subsequent write operations. The base address auto increments by one for each byte of data written after the data byte intended for the base address.
When the serial interface is inactive (SCL and SDA are HIGH) communications are initiated by sending a start signal. The start signal is a HIGH-to-LOW transition on SDA while SCL is HIGH. This signal alerts all slaved devices that a data transfer sequence is coming. The first eight bits of data transferred after a start signal comprise a seven bit slave address and a single R/W bit. The R/W
SDA / R/W tBUFF tSTAH SCL / CS tBAH
65-6294-28
tDHO tDAL
tDSU
tSTASU
tSTOSU
Figure 25. Serial Port Read/Write Timing
Data are read from the control registers of the TMC2192 in a similar manner. Reading requires two data transfer operations: The base address must be written with the R/W bit of the slave address byte LOW to set up a sequential read operation.
Reading (the R/W bit of the slave address byte HIGH) begins at the previously established base address. The address of the read register auto increments after each byte is transferred. To terminate a write sequence to the TMC2192, a stop signal must be sent. A stop signal comprises a LOW-to-HIGH transition of SDA while SCL is HIGH. To terminate a read
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31
TMC2192
PRODUCT SPECIFICATION
sequence simply do not acknowledge (NOACK) the last byte received and the TMC2192 will terminate the sequence. A repeated start signal occurs when the master device driving the serial interface generates a start signal without first
generating a stop signal to terminate the current communication. This is used to change the mode of communication (read, write) between the slave and master without releasing the serial interface lines.
SDA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ACK
SCL
65-6294-29
Figure 26. Serial Interface - Typical Byte Transfer
SDA
A6
A5
A4
A3
A2
SA1
SA0
R/W
ACK
SCL
65-6294-30
Figure 27. Serial Interface - Chip Address
Serial Interface Read/Write Examples
Write to one control register * Start signal * Slave Address byte (R/W bit = LOW) * Block Pointer (00) * Offset Pointer * Data byte to base address * Stop signal Write to four consecutive control registers * Start signal * Slave Address byte (R/W bit = LOW) * Block Pointer (00) * Offset Pointer * Data byte to base address * Data byte to (base address + 1) * Data byte to (base address + 2) * Data byte to (base address + 3) * Stop signal Write to one OLUT location * Start signal * Slave Address byte (R/W bit = LOW) * Block Pointer (01) * Offset Pointer (base address) * Data byte to base address (Y) * Data byte to base address (Cb) * Data byte to base address (Cr) * Stop signal
Write to four consecutive OLUT locations * Start signal * Slave Address byte (R/W bit = LOW) * Block Pointer (01) * Offset Pointer (base address) * Data byte to base address (Y) * Data byte to base address (Cb) * Data byte to base address (Cr) * Data byte to base address +1 (Y) * Data byte to base address +1 (Cb) * Data byte to base address +1 (Cr) * Data byte to base address +2 (Y) * Data byte to base address +2 (Cb) * Data byte to base address +2 (Cr) * Data byte to base address +3 (Y) * Data byte to base address +3 (Cb) * Data byte to base address +3 (Cr) * Stop signal Read from one control register * Start signal * Slave Address byte (R/W bit = LOW) * Block Pointer (00) * Offset Pointer * Stop signal * Start signal * Slave Address byte (R/W bit = HIGH) * Data byte from base address * NOACK
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PRODUCT SPECIFICATION
TMC2192
Read from four consecutive control registers * Start signal * Slave Address byte (R/W bit = LOW) * Block Pointer (00) * Offset Pointer * Stop signal * Start signal
* * * * * *
Slave Address byte (R/W bit = HIGH) Data byte from base address Data byte from (base address + 1) Data byte from (base address + 2) Data byte from (base address + 3) NOACK
Control Register Map
Table 22. Control Register Map Reg Bit 00 01 02 03 04 04 04 04 05 05 05 05 05 06 06 06 06 06 07 07 07 07 07 07 07 08 09 7-0 7-0 7-0 7-0 7-4 3 2 1-0 7 6 5-4 3-2 1-0 7-6 5-3 2 1 0 7 6 5 4-3 2 1 0 7-0 7 Mnemonic PARTID2 PARTID1 PARTID0 REVID Reserved SRESET SKEN PDRM D1OFF Reserved INMODE OMIX SOURCE FORMAT MODE PDCDIR TOUT TSOUT LDFID SKFLIP DDSRST Reserved ANCFREN ANCPHEN ANCTREN ANCID HKEN Ancillary Frequency Enable Ancillary Phase Enable Ancillary Timing Enable Ancillary Data Identification Hardware KEY Enable Function Reads back 97h Reads back 21h Reads back 92h Silicon revision # Set to Low Software RESET Data KEY Enable Pixel Data Ramping Mode Input Format Register YCBCR Input Formatting Program Low Input Mode Select Overlay Mixer Select Video Input Select 0F 7-0 FKEYMIN Video Format Video Mode PDC Directional Control External Sync Output Control External Sync Delay Control Field Lock Select Soft Key Inversion DDS Reset 10 10 10 10 10 10 11 11 11 11 11 11 11 11 7 6 5 4-3 2 1-0 7 6 5 4 3 2 1 0 0E 7-0 FKEYMAX 0B 0C 0D 7-0 DKEYMIN 7-0 EKEYMAX 7-0 EKEYMIN 0A Table 22. Control Register Map (continued) Reg Bit 09 09 09 09 09 09 6 5 4 3 2 1-0 Mnemonic BUKEN SKEXT DKDIS EKDIS FKDIS LAYMODE Function Burst KEY Enable Data KEY Operation Select Green/Y Data KEY Disable Blue/CB Data KEY Disable Red/CR Data KEY Disable Layer Assignment Select Green/Y Maximum Data Key Value Green/Y Minimum Data Key Value Blue/CB Maximum Data Key Value Blue/CB Minimum Data Key Value Red/CR Maximum Data Key Value Red/CR Minimum Data Key Value D/A #4 Disable D/A #3 Disable D/A #2 Disable Set to 0. Overlay LUT Disable Program Low DRS Selection Program Low Composite 2 Overflow Control X/Sin(x) Filter Enable Program Low Luma Disable Chroma Disable Burst Disable Key Value Registers 7-0 DKEYMAX
TMC2192 Identification Registers (Read only)
Gamma Filters Register
General Control Register
DAC Control Registers COMPDIS CHROMADIS LUMADIS Reserved OLUTDIS Reserved DRSSEL Reserved COMP2DB SINEN Reserved LUMDIS CHRMDIS BURSTDIS
Horizontal Ancillary Data Control Register
Ancillary Data ID Register Keying/Overlay Engine
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33
TMC2192
PRODUCT SPECIFICATION
Table 22. Control Register Map (continued) Reg Bit 14 15 16 17 17 7-0 7-0 7-0 7-1 0 Mnemonic VBIPEDEM VBIPEDEL VBIPEDOM VBIPEDOL HVA Function VBI Pedestal Enable, Even Fields VBI Pedestal Enable, Even Fields VBI Pedestal Enable, Odd Fields VBI Pedestal Enable, Odd Fields Horizontal and Vertical Sync Alignment Program Low Genlock Control Register 1 Genlock Control Register 0 VBI Active Video Enable, Field 1 Test Register EH/SL Offset Control Bit Half Line Enable VBI Active Video Enable, Field 2 Program Low Composite Pedestal Height First Byte of CC Data Second Byte of CC Data Enable CC Data Packet Request to Send Data Auto Parity Generation CC Field Select CC Line Select Timing Registers 1F 20 21 22 23 7-0 7-0 7-0 7-0 7-0 PDCNT SY BR BU CBP Pixel Data Control Start Horizontal Sync Tip Duration Breezeway Duration Burst Duration Color Back Porch Duration
Table 22. Control Register Map (continued) Reg Bit 24 25 26 27 28 29 2A 2B 2C 2D 2D 2D 2D 2E 2E 2F 30 31 32 33 34 35 36 37 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-6 5-4 3-2 1-0 7-5 4-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 Mnemonic XBP VA VC VB EL EH SL SH FP XBP VA VB VC FIELD LTYPE CBL MCF1L Reserved Reserved MCF2L Reserved MCF3L Reserved Reserved Function Extended Color Back Porch Duration Active Video Region Duration Active Video Region 2nd Half Line Duration Active Video Region 1st Half Line Duration Equalization Pulse Low Duration Equalization Pulse High Duration Vertical Sync Pulse Low Duration Vertical Sync Pulse High Duration Front Proch Duration Extended Color Back Porch Duration Active Video Duration Active Video Region 1st Half Line Duration Active Video Region 2nd Half Line Duration Field Identification (read only) Line Type Identification (read only) Color Bar Duration Matrix Coefficient #1 Program Low Program Low Matrix Coefficient #2 Program Low Matrix Coefficient #3 Program Low Program Low
VBI Ped Enable Registers
Vertical Blanking Interval Enable Registers 18 18 18 18 19 19 19 19 1A 1A 1C 1D 1E 1E 1E 1E 1E 7 6 5 4-0 7 6 5 4-0 7 6-0 7-0 7-0 7 6 5 4 3-0 Reserved GLKCTL1 GLKCTL0 VBIENF1 SHORT T512 HALFEN VBIENF2 Reserved PEDHGT1 CCD1 CCD2 CCON CCRTS CCPAR CCFLD CCLINE
Pedestal Height Register
Closed Caption Registers
Color Space Matrix Registers
34
REV. 1.0.0 8/13/03
PRODUCT SPECIFICATION
TMC2192
Table 22. Control Register Map (continued) Reg Bit 38 39 3A 3A 3B 3B 3C 3C 3D 3D 3E 3E 3F 3F 3F 3F 3F 3F 7-0 7-0 7-4 3-0 7-3 2-0 7-3 2-0 7-4 3-0 7-4 3-0 7 6 5 4 3 2-0 Mnemonic Reserved Reserved MCF1M Reserved Reserved MCF4M Reserved MCF6M Reserved Reserved Reserved Reserved SEL_CLK Reserved GAUSS_BVP SEL_PIX C2DB_OFF Reserved Function Program Low Program Low Matrix Coefficient #1 Program Low Set to 0. Matrix Coefficient #4 Set to 0. Matrix Coefficient #6 Program Low Program Low Program Low Program Low DCVBS Clock Select Program Low Gaussian Bypass Select DCVBS Output Selection COMP2DB Offset Selection Program Low
Table 22. Control Register Map (continued) Reg Bit 40 41 42 43 44 45 46 47 48 49 4A 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 Mnemonic FREQL FREQ3 FREQ2 FREQM SYSPHL SYSPHM BURPHL BURPHM BRSTFULL BRST1 BRST2 Function Subcarrier Frequency Subcarrier Frequency Subcarrier Frequency Subcarrier Frequency System Phase System Phase Burst Phase Burst Phase Burst Height - Maximum Amplitude Burst Height - 1st Intermediate Value Burst Height - 2nd Intermediate Value
Subcarrier Registers
Note: 1. For each register listed above, all bits not specified are reserved and should be set to logic LOW to ensure proper operation.
Control Register Definitions
Part Identification Register (0x00) 7 6 5 4 PARTID2 Reg 00 Bit 7-0 Name PARTID2 Description (Read Only) 0x97 3 2 1 0
Part Identification Register (0x01) 7 6 5 4 PARTID1 Reg 01 Bit 7-0 Name PARTID1 Description (Read Only) 0x21 3 2 1 0
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TMC2192
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Part Identification Register (0x02) 7 6 5 4 PARTID0 Reg 02 Bit 7-0 Name PARTID0 Description (Read Only) 0x92 3 2 1 0
Revision Identification Register (0x03) 7 6 5 4 REVID0 Reg 03 Bit 7-0 Name REVID0 Description Reads back the revision number of the part. 3 2 1 0
Gamma Filters Register (0x04) 7 RESERVED Reg 04 04 Bit 7-4 3 6 RESERVED Name RESERVED SRESET 5 RESERVED 4 RESERVED 3 SRESET 2 SKEN 1 PDRM 0
Description Set to Low Software RESET. When LOW, resets internal state machines and disables outputs. When HIGH, state machines are active and outputs are enabled. Data KEY Enable. When SKEN is LOW, Data keying is disabled. When SKEN is HIGH, Data keying is enabled. Pixel Data Ramping Mode. Pixel Data weighting for the rising edge of active video. NTSC: 0 0 1/8 1/2 7/8 1 1 PAL: 0 1/8 3/8 5/8 7/8 1 1 00 Pixels are weighted on the edge. 01 Sample and hold the 5th pixel for the slope weighting 1X Hard switch 0 0 0 1 1 1
04
2
SKEN
04
1-0
PDRM
36
REV. 1.0.0 8/13/03
PRODUCT SPECIFICATION
TMC2192
Control Register Definitions (continued)
Input Format Register (0x05) 7 D10FF Reg 05 Bit 7 Name D1OFF 6 5 INMODE Description YCBCR Input Formatting. When D1OFF is HIGH, 64 is subtracted from Y data path of the PD port. When D1OFF is LOW, pixel data is passed through. Program Low Input Mode Select. 00 24 bit YCBCR (4:4:4) 01 10 bit D1 (YCBCR) 10 20 bit YCBCR (4:4:4) 11 20 bit YCBCR (4:2:2) PD[7:0] = Y PD[23:16] = CB PD[15:8] = CR PD[23:14] = YCBCR at 27MHz PD[9:0] = Y PD[23:14] = CBCR (at 27MHz) PD[9:0] = Y PD[23:14] = CBCR 4 3 OMIX 2 1 SOURCE 0
05 05
6 5-4
Reserved INMODE
05
3-2
OMIX
Overlay Mixer Select. 00 No mix - PD data is always passed 01 Hard mix - mixer performs a hard switch between PD and Overlay 10 Set1 mix - the pixel data has the following weighting on the transition; 0, 1/2, 1 11 Set2 mix - the pixel data has the following weighting on the transition; 0, 1/8, 1/2, 7/8, 1 Video Input Select. Chooses from internal test patterns or pixel data port. 00 PD PORT 01 Modulated Ramp 10 INTERNAL COLOR BAR (75%) 11 INTERNAL COLOR BAR (100%)
05
1-0
SOURCE
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37
TMC2192
PRODUCT SPECIFICATION
Control Register Definitions (continued)
General Control Register (0x06) 7 FORMAT Reg 06 Bit 7-6 Name FORMAT 6 5 4 MODE Description Video Format. 00 NTSC 01 PAL - B,G,H,I,N 10 PAL - M 11 Reserved Video Mode. 000 MASTER with free-running subcarrier 001 SLAVE with free-running subcarrier 010 CCIR656 with free-running subcarrier 011 GENLOCK with subcarrier phase and frequency locked to the GRS information. 100 MASTER with subcarrier phase reset every 8 fields 101 SLAVE with subcarrier phase reset every 8 fields 110 CCIR656 with subcarrier phase reset every 8 fields. 111 DRS-Lock with subcarrier phase and frequency locked to the DRS information. PDC Directional Control. When PDC is LOW, the PDC pin is an output. When PDCDIR is HIGH, the PDC pin is an input that can override the internally generated PDC and blank the active video of a line. External Sync Output Control. When TOUT = LOW, a MPEG style field toggle is the output on pin VSOUT. When TOUT = HIGH, a traditional vertical sync is the output on pin VSOUT. External Sync Delay Control. When the TSOUT is LOW, HSOUT, VSOUT are delayed to match propagation delay through the chip. When TSOUT is HIGH, HSOUT, VSOUT are aligned with the incoming data on the PD port. 3 2 PDCDIR 1 TOUT 0 TSOUT
06
5-3
MODE
06
2
PDCDIR
06
1
TOUT
06
0
TSOUT
38
REV. 1.0.0 8/13/03
PRODUCT SPECIFICATION
TMC2192
Control Register Definitions (continued)
Horizontal Ancillary Data Control Register (0x07) 7 LDFID Reg 07 Bit 7 6 SKFLIP Name LDFID 5 DDSRST Description Field Lock Select. When LDFID is HIGH, the FLD[2:0] pins are used as inputs to lock the field the that the TMC2192 is encoding. 5 PXCK's after the falling edge of HSIN the FLD[2:0] pins are sampled. When LDFID is LOW, the FLD[2:0] pins output the current field that is being encoded. Soft Key Inversion. When SKFLP is LOW, the key generated by the data keying is a normal state. When SKFLP is HIGH, the key generated by the data keying is a inverted state. DDS Reset. By inserting a logic HIGH into this register the DDS accumulator is reset to SYSPH value at the start of the next field 1 and DDSRST is reset LOW. This enables the DDS to be reset when the encoder is operating with a free running subcarrier. Ancillary Frequency Enable. When HIGH, the encoder gets subcarrier frequency data (FREQ3-0) from incoming ancillary data (in accordance with FRV bit). When LOW, FREQ3-0 registers contain the subcarrier frequency data. Ancillary Phase Enable. When HIGH, the encoder gets subcarrier phase offset data (SCHPHL and SCHPHM) from incoming ancillary data (in accordance with PHV bit). When LOW, a default value of 0000h is used for subcarrier phase. Ancillary Timing Enable. When HIGH, the encoder decodes incoming ancillary data to determine video timing (FIELD and SVF). When LOW, the ancillary timing reference data is ignored. 4 RESERVED 3 2 ANCFREN 1 ANCPHEN 0 ANCTREN
07
6
SKFLIP
07
5
DDSRST
07 07
4-3 2
RESERVED ANCFREN
07
1
ANCPHEN
07
0
ANCTREN
Ancillary Data ID Register (0x08) 7 6 5 4 ANCID Reg 08 Bit 7-0 Name ANCID Description Ancillary Data Identification. Bits 7-0 determine the ancillary data identification. Bit 0 is an odd parity bit. The value in this register must match that of the incoming ancillary data. 3 2 1 0
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TMC2192
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Keying/Overlay Engine Register (0x09) 7 HKEN Reg 09 Bit 7 6 BUKEN Name HKEN 5 SKEXT 4 DKDIS 3 EKDIS 2 FKDIS 1 LAYMODE 0
Description Hardware KEY Enable. When LOW, the KEY pin is ignored. When HIGH, the KEY pin is enabled. Burst KEY Enable. When LOW, the output video burst is generated internally. When HIGH, the output video burst is taken from the CVBS port. Data KEY Operation Select. When LOW, data keying is allowed only during active video window. When HIGH, data keying is allowed during frame. Y Data KEY Disable. When LOW, Y input data is enabled for data keying. When HIGH, Y input data is ignored for data keying. CB Data KEY Disable. When LOW, CB input data is enabled for data keying. When HIGH, CB input data is ignored for data keying. CR Data KEY Disable. When LOW, CR input data is enabled for data keying. When HIGH, CR input data is ignored for data keying. Layer Assignment Select. BACKGND Source PD PD CVBS CVBS MIDGND Source OVERLAY CVBS OVERLAY PD FOREGND Source CVBS OVERLAY PD OVERLAY
09
6
BUKEN
09
5
SKEXT
09
4
DKDIS
09
3
EKDIS
09
2
FKDIS
09
1-0
LAYMODE
Mode 0 1 2 3
Key 0L4-0 KEY OL4-0 KEY
Key KEY OL4-0 KEY OL4-0
40
REV. 1.0.0 8/13/03
PRODUCT SPECIFICATION
TMC2192
Control Register Definitions (continued)
Key Value Register (0x0A) 7 6 5 4 DKEYMAX Reg 0A Bit 7-0 Name DKEYMAX Description Y Maximum Data Key Value. DKEYMAX is compared against the 8 MSB's of Y channel. If DKEYMAX is greater or equal to Y and DKEYMIN less than Y then a match is signaled. 3 2 1 0
Key Value Register (0x0B) 7 6 5 4 DKEYMIN Reg 0B Bit 7-0 Name DKEYMIN Description Y Minimum Data Key Value. DKEYMIN is compared against the 8 MSB's of Y channel. If DKEYMAX is greater or equal to Y and DKEYMIN less than Y then a match is signaled. 3 2 1 0
Key Value Register (0x0C) 7 6 5 4 EKEYMAX Reg 0C Bit 7-0 Name EKEYMAX Description CB Maximum Data Key Value. EKEYMAX is compared against the 8 MSB's of CB channel. If EKEYMAX is greater or equal to CB and EKEYMIN less than CB then a match is signaled. 3 2 1 0
Key Value Register (0x0D) 7 6 5 4 EKEYMIN Reg 0D Bit 7-0 Name DKEYMIN Description CB Minimum Data Key Value. EKEYMIN is compared against the 8 MSB's of CB channel. If EKEYMAX is greater or equal to CB and EKEYMIN less than CB then a match is signaled 3 2 1 0
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41
TMC2192
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Key Value Register (0x0E) 7 6 5 4 FKEYMAX Reg 0E Bit 7-0 Name FKEYMAX Description CR Maximum Data Key Value. FKEYMAX is compared against the 8 MSB's of CR channel. If FKEYMAX is greater or equal to CR and FKEYMIN less than CR then a match is signaled. 3 2 1 0
Key Value Register (0x0F) 7 6 5 4 FKEYMIN Reg 0F Bit 7-0 Name FKEYMIN Description CR Minimum Data Key Value. FKEYMIN is compared against the 8 MSB's of CR channel. If FKEYMAX is greater or equal to CR and FKEYMIN less than CR then a match is signaled. 3 2 1 0
42
REV. 1.0.0 8/13/03
PRODUCT SPECIFICATION
TMC2192
Control Register Definitions (continued)
DAC Control Register (0x10) 7 COMPDIS Reg 10 Bit 7 6 CHROMADIS Name COMPDIS 5 LUMADIS 4 RESERVED 3 RESERVED 2 OLUTDIS 1 RESERVED 0
Description Composite D/A Disable. When COMPDIS is LOW, the COMPOSITE D/A is enabled. When COMPDIS is HIGH, the COMPOSITE D/A is disabled. Chroma D/A Disable. When CHROMADIS is LOW, the CHROMA D/A is enabled. When CHROMADIS is HIGH, the CHROMA D/A is disabled. LUMA D/A Disable. When LUMADIS is LOW, the LUMA D/A is enabled. When LUMADIS is HIGH, the LUMA D/A is disabled. Set to 0. Overlay LUT Disable. When OLUTDIS is LOW, the olut is enabled. When OLUTDIS is HIGH, the olut is disabled. Program Low
10
6
CHROMADIS
10
5
LUMADIS
10 10
4-3 2
RESERVED OLUTDIS
10
1-0
RESERVED
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TMC2192
PRODUCT SPECIFICATION
Control Register Definitions (continued)
DAC Control Register (0x11) 7 DRSSEL Reg 11 Bit 7 6 RESERVED Name DRSSEL 5 COMP2DB 4 SINEN 3 REFSEL 2 LUMDIS 1 CHRMDIS 0 BURSTDIS
Description DRS Selection. When DRSSEL is HIGH, PD[7:0] is routed to the DRS detection block. When DRSSEL is LOW, CVBS[9:2] is routed to the DRS detection block. Program Low Composite 2 Overflow Control. When COMP2DB is HIGH, the digital range of the composite sumer is 0 to 2047 with half the digital resolution. When COMP2DB is LOW, the digital output of the composite summer is 0 to 1023, all values exceeding 1023 or below 0 are clipped. X/Sine(X) Filter Enable. When SINEN is LOW, the X/Sin(X) filter is bypassed. When SINEN is HIGH, the X/Sin(X) filter is used to compensate for the DAC roll-off at high frequencies. Program Low Luma Disable. When LUMDIS is LOW, the luminance data on the composite data path is enabled. When LUMDIS is HIGH, the luminance data on the composite data path is disabled. Chroma Disable. When CHRMDIS is LOW, the chrominance data on the composite data path is enabled. When CHRMDIS is HIGH, the chrominance data on the composite data path is disabled. Burst Disable. When BURSTDIS is LOW, the burst is enabled. When BURSTDIS is HIGH, the burst is disabled.
11 11
6 5
RESERVED COMP2DB.
11
4
SINEN
11 11
3 2
RESERVED LUMDIS
11
1
CHRMDIS
11
0
BURSTDIS
44
REV. 1.0.0 8/13/03
PRODUCT SPECIFICATION
TMC2192
Control Register Definitions (continued)
VBI Ped Enable Register (0x14) 7 6 5 4 VBIPEDEM Reg 14 Bit 7-0 Name VBIPEDEM Description VBI Pedestal Enable, Even Fields. VBIPEDEM is the bits 15-8 of VBIPEDE[15:0]. VBIPEDE controls the addition of pedestal on a line by line basis from line 10 in NTSC (VBIPEDE[0] = HIGH) to line 24 (VBIPEDE[14] = HIGH) in the EVEN field of NTSC. VBIPEDE[15] controls the pedestal from line 25 to line 263 inclusive. 3 2 1 0
VBI Ped Enable Register (0x15) 7 6 5 4 VBIPEDEL Reg 15 Bit 7-0 Name VBIPEDEL Description VBI Pedestal Enable, Even Fields. VBIPEDEL is the bits 7-0 of VBIPEDE[15:0]. VBIPEDE controls the addition of pedestal on a line by line basis from line 10 in NTSC (VBIPEDE[0] = HIGH) to line 24 (VBIPEDE[14] = HIGH) in the EVEN field of NTSC. VBIPEDE[15] controls the pedestal from line 25 to line 263 inclusive. 3 2 1 0
VBI Ped Enable Register (0x16) 7 6 5 4 VBIPEDOM Reg 16 Bit 7-0 Name VBIPEDOM Description VBI Pedestal Enable, Odd Fields. VBIPEDOM is the bits 14-7 of VBIPEDO[14:0]. VBIPEDO controls the addition of pedestal on a line by line basis from line 273 (VBIPEDE[0] = HIGH) to line 286 (VBIPEDE[13] = HIGH) in the ODD field of NTSC. VBIPEDO[14] controls the pedestal from line 287 to line 525 inclusive. 3 2 1 0
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45
TMC2192
PRODUCT SPECIFICATION
Control Register Definitions (continued)
VBI Ped Enable Register (0x17) 7 6 5 4 VBIPEDOL Reg 17 Bit 7-1 Name VBIPEDOM Description VBI Pedestal Enable, Odd Fields. VBIPEDOL is the bits 6-0 of VBIPEDO[14:0]. VBIPEDO controls the addition of pedestal on a line by line basis from line 273 (VBIPEDE[0] = HIGH) to line 286 (VBIPEDE[13] = HIGH) in the ODD field of NTSC. VBIPEDO[14] controls the pedestal from line 287 to line 525 inclusive. Horizontal and Vertical Sync Alignment. When HVA is LOW, the falling edge of HSIN and VSIN must occur just prior to the rising edge of PXCK to start an field 1. When HVA is HIGH, VSIN is allowed to vary from HSIN by 32 pixels. 3 2 1 0 HVA
17
0
HVA
Vertical Blanking Interval Enable Register (0x18) 7 Reserved Reg 18 18 Bit 7 6 6 GLKCTL1 Name Reserved GLKCTL1 Genlock Control Register 1. When GLKCTL1 is LOW, the PALODD bit of the GRS stream is ignored. When GLKCTL1 is HIGH, the PALODD bit of the GRS stream controls the PALODD flip of the subcarrier. Genlock Control Register 0. When GLKCTL0 is LOW, the Color Frame bit of the GRS stream is ignored. When GLKCTL0 is HIGH, the Color Frame bit of the GRS stream controls the field sequence in the FVHGEN. VBI Active Video Enable, Field 1. The value of VBIENF1 determines which line blanking stops and active line for EVEN fields in NTSC starting from line 4 to line 35 or an ODD fields for PAL starting from line 1 to line 32. 5 GLKCTL0 Description 4 3 2 VBIENF1 1 0
18
5
GLKCTL0
18
4-0
VBIENF
46
REV. 1.0.0 8/13/03
PRODUCT SPECIFICATION
TMC2192
Control Register Definitions (continued)
Vertical Blanking Interval Enable Register (0x19) 7 SHORT Reg 19 19 Bit 7 6 6 T512 Name SHORT T512 5 HALFEN Description Test Register. Program LOW. EH/SL Offset Control Bit. When LOW, the true value of EH and SL is offset by 256. When HIGH, the true value of EH and SL is offset by 512. Half Line Enable. When LOW, half-line blanking occurs on line 283 (NTSC) or line 23 (PAL). When HIGH, line 283 (NTSC) or line 23 (PAL) is treated as a full line of active video. VBI Active Video Enable, Field 2. The value of VBIENF2 determines which line blanking stops and active line for ODD fields in NTSC starting from line 4 to line 35 or an EVEN fields for PAL starting from line 1 to line 32. 4 3 2 VBIENF2 1 0
19
5
HALFEN
19
4-0
VBIENF2
Pedestal Height Register (0x1A) 7 Reserved Reg 1A 1A Bit 7 6-0 Name Reserved PEDHGT1 Composite Pedestal Height. PEDHGT1 is a 2's comp value producing a pedestal height from -22.1 IRE to 21.7 IRE with .345 IRE steps on the composite data path. The default 7.5 IRE pedestal for NTSC-M results from a hex code of 0010110b. Description 6 5 4 3 PEDHGT1 2 1 0
Closed Caption Register (0x1C) 7 6 5 4 CCD1 Reg 1C Bit 7-0 Name CCD1 Description First Byte of CC Data. Bit 0 is the LSB. The MSB will be overwritten by an ODD Parity Bit if CCPAR is HIGH. 3 2 1 0
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TMC2192
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Closed Caption Register (0x1D) 7 6 5 4 CCD2 Reg 1D Bit 7-0 Name CCD2 Description Second Byte of CC Data. Bit 0 is the LSB. The MSB will be overwritten by an ODD Parity Bit if CCPAR is HIGH 3 2 1 0
Closed Caption Register (0x1E) 7 CCON Reg 1E Bit 7 6 CCRTS Name CCON 5 CCPAR 4 CCFLD 3 2 CCLINE 1 0
Description Enable CC Data Packet. Command the CC data generator to send either CC data or a NULL byte whenever the specified line is transmitted. Request To Send Data. This bit is set HIGH by the user when bytes 0x1C and 0x1D have been loaded with the next two bytes to be sent. When the encoder's line count reaches preceding the line specified in bits 4-0 of this register the data will be transferred from registers 0x1C and 0x1D, and RTS will be RESET LOW. A new pair of bytes may then be loaded into registers 0x1C and 0x1D. If CCON = 1 and CCRTS = 0 when the CC line is to be sent, NULL bytes will be sent. Auto Parity Generation. When set HIGH, the encoder replaces the MSB of bytes 0x1C and 0x1D with a calculated ODD parity. When set LOW, the CC processor transmits the 16 bits exactly as loaded into registers 0x1C and 0x1D. CC Field Select. When LOW, CC data is transmitted on the selected line of ODD fields. When HIGH, it is sent on EVEN fields. CC Line Select. Defines (with an offset) the line on which CC data are transmitted.
1E
6
CCRTS
1E
5
CCPAR
1E
4
CCFLD
1E
3-0
CCLINE
Timing Register (0x1F) 7 6 5 4 PDCNT Reg 1F Bit 7-0 Name PDCNT Description Pixel Data Control Start. PDCNT determines the number of pixels (PCK's) from the midpoint of the falling edge of horizontal sync to the rising edge of PDC on active video lines. 3 2 1 0
48
REV. 1.0.0 8/13/03
PRODUCT SPECIFICATION
TMC2192
Control Register Definitions (continued)
Timing Register (0x20) 7 6 5 4 SY Reg 20 Bit 7-0 Name SY Description Horizontal Sync Tip Duration. This 8 bit register holds a value extending from 0 to 255 PCK cycles. 3 2 1 0
Timing Register (0x21) 7 6 5 4 BR Reg 21 Bit 7-0 Name BR Description Breezeway Duration. This 8 bit register holds a value extending from 0 to 255 PCK cycles. 3 2 1 0
Timing Register (0x22) 7 6 5 4 BU Reg 22 Bit 7-0 Name BU Description Burst Duration. This 8 bit register holds a value extending from 0 to 255 PCK cycles. 3 2 1 0
Timing Register (0x23) 7 6 5 4 CBP Reg 23 Bit 7-0 Name CBP Description Color Back Porch Duration. This 8 bit register holds a value extending from 0 to 255 PCK cycles. 3 2 1 0
Timing Register (0x24) 7 6 5 4 XBP Reg 24 Bit 7-0 Name CBP Description Extended Color Back Porch Duration. This 8 bit register holds the LSB's of a 10 bit value extending from 0 to 1023 PCK cycles. 49 3 2 1 0
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TMC2192
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Timing Register (0x25) 7 6 5 4 VA Reg 25 Bit 7-0 Name VA Description Active Video Region Duration. This 8 bit register holds the LSB's of a 10 bit value extending from 0 to 1023 PCK cycles. 3 2 1 0
Timing Register (0x26) 7 6 5 4 VC Reg 26 Bit 7-0 Name VC Description Active Video Region 2nd Half Line Duration. This 8 bit register holds the LSB's of a 10 bit value extending from 0 to 1023 PCK cycles. 3 2 1 0
Timing Register (0x27) 7 6 5 4 VB Reg 27 Bit 7-0 Name VB Description Active Video Region 1st Half Line Duration. This 8 bit register holds the LSB's of a 10 bit value extending from 0 to 1023 PCK cycles. 3 2 1 0
Timing Register (0x28) 7 6 5 4 VB Reg 28 Bit 7-0 Name EL Description Equalization Pulse Low Duration. This 8 bit register holds a value extending from 0 to 255 PCK cycles. 3 2 1 0
50
REV. 1.0.0 8/13/03
PRODUCT SPECIFICATION
TMC2192
Control Register Definitions (continued)
Timing Register (0x29) 7 6 5 4 EH Reg 29 Bit 7-0 Name EH Description Equalization Pulse High Duration. This 8 bit register holds 8 LSB's of EH, The addition of 256 or 512 is controlled by T512. The range is either 256 to 511 PCK cycles or 512 to 767 PCK cycles. 3 2 1 0
Timing Register (0x2A) 7 6 5 4 SL Reg 2A Bit 7-0 Name SL Description Vertical Sync Pulse Low Duration. This 8 bit register holds 8 LSB's of SL, The addition of 256 or 512 is controlled by T512. The range is either 256 to 511 PCK cycles or 512 to 767 PCK cycles. 3 2 1 0
Timing Register (0x2B) 7 6 5 4 SH Reg 2B Bit 7-0 Name SH Description Vertical Sync Pulse High Duration. This 8 bit register holds a value extending from 0 to 255 PCK cycles. 3 2 1 0
Timing Register (0x2C) 7 6 5 4 FP Reg 2C Bit 7-0 Name FP Description Front Porch Duration. This 8 bit register holds a value extending from 0 to 255 PCK cycles. 3 2 1 0
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TMC2192
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Timing Register (0x2D) 7 XBP Reg 2D 2D 2D 2D Bit 7-6 5-4 3-2 1-0 Name XBP VA VB VC 6 5 VA Description Extended Color Back Porch Duration. 2 MSB's of the 10 bit XBP, extending from 0 to 1023 PCK cycles. Active Video Duration. 2 MSB's of the 10 bit VA, extending from 0 to 1023 PCK cycles. Active Video Region 1st Half Line Duration. 2 MSB's of a 10 bit VB, extending from 0 to 1023 PCK cycles. Active Video Region 2nd Half Line Duration. 2 MSB's of a 10 bit VC, extending from 0 to 1023 PCK cycles. 4 3 VB 2 1 VC 0
Timing Register (0x2E) 7 6 FIELD Reg 2E Bit 7-5 Name FIELD Description Field Identification. (READ ONLY) These three bits are updated 12 PXCK periods after each vertical sync. They allow the user to determine field type on a continuous basis LineType Identification (READ ONLY) These three bits are updated 5 PXCK periods after each horizontal sync. They allow the user to determine line type on a continuous basis. 5 4 3 2 LTYPE 1 0
2E
4-0
LTYPE
Timing Register (0x2F) 7 6 5 4 CBL Reg 2F Bit 7-0 Name CBL Description Color Bar Duration. This 8 bit register holds a value extending from 0 to 255 PCK cycles. 3 2 1 0
Color Space Matrix Register (0x30) 7 6 5 4 MCF1L Reg 30 Bit 7-0 Name MCF1L Description Matrix Coefficient #1. Bits 7-0 of MCF1. 3 2 1 0
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PRODUCT SPECIFICATION
TMC2192
Control Register Definitions (continued)
Color Space Matrix Register (0x31) 7 6 5 4 RESERVED Reg 31 Bit 7-0 Name RESERVED Description Program Low 3 2 1 0
Color Space Matrix Register (0x32) 7 6 5 4 RESERVED Reg 32 Bit 7-0 Name RESERVED Description Program Low 3 2 1 0
Color Space Matrix Register (0x33) 7 6 5 4 MCF2L Reg 33 Bit 7-0 Name MCF2L Description Matrix Coefficient #2. Bits 7-0 of MCF4. 3 2 1 0
Color Space Matrix Register (0x34) 7 6 5 4 RESERVED Reg 34 Bit 7-0 Name RESERVED Description Program Low 3 2 1 0
Color Space Matrix Register (0x35) 7 6 5 4 MCF3L Reg 35 Bit 7-0 Name MCF3L Description Matrix Coefficient #3. Bits 7-0 of MCF6. 3 2 1 0
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TMC2192
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Color Space Matrix Register (0x36) 7 6 5 4 RESERVED Reg 36 Bit 7-0 Name RESERVED Description Program Low 3 2 1 0
Color Space Matrix Register (0x37) 7 6 5 4 RESERVED Reg 37 Bit 7-0 Name RESERVED Description Program Low 3 2 1 0
Color Space Matrix Register (0x38) 7 6 5 4 RESERVED Reg 38 Bit 7-0 Name RESERVED Description Program Low 3 2 1 0
Color Space Matrix Register (0x39) 7 6 5 4 RESERVED Reg 39 Bit 7-0 Name RESERVED Description Program Low 3 2 1 0
Color Space Matrix Register (0x3A) 7 6 MCF1M Reg 3A 3A Bit 7-4 3-0 Name MCF1M RESERVED Description Matrix Coefficient #1. Bits 11-8 of MCF1. Program Low 5 4 3 2 MCF2M 1 0
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PRODUCT SPECIFICATION
TMC2192
Control Register Definitions (continued)
Color Space Matrix Register (0x3B) 7 6 MCF3M Reg 3B 3B Bit 7-3 2-0 Name RESERVED MCF4M Description Set to 0. Matrix Coefficient #4. Bits 10-8 of MCF4. 5 4 3 RESERVED 2 1 MCF4M 0
Color Space Matrix Register (0x3C) 7 6 MCF5M Reg 3C 3C Bit 7-3 2-0 Name RESERVED MCF6M Description Set to 0. Matrix Coefficient #6. Bits 10-8 of MCF6. 5 4 3 RESERVED 2 1 MCF6M 0
Color Space Matrix Register (0x3D) 7 6 RESERVED Reg 3D 3D Bit 7-4 3-0 Name RESERVED RESERVED Description Program Low Program Low 5 4 3 2 RESERVED 1 0
Color Space Matrix Register (0x3E) 7 6 RESERVED Reg 3E 3E Bit 7-4 3-0 Name RESERVED RESERVED Description Program Low Program Low 5 4 3 2 RESERVED 1 0
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TMC2192
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Color Space Matrix Register (0x3F) 7 SEL_CLK Reg 3F Bit 7 6 RESERVED Name SEL_PIX 5 GAUSS_BYP 4 SEL_PIX 3 C2DB_OFF 2 NMEH 1 CSMFMT 0
Description DCVBS Output Selection. When SEL_PIX is HIGH, the interpolated pixel data is selected as the output for the DCVBS port. When SEL_PIX is LOW, the non-interpolated pixel data is selected as the output for the DCVBS port. Program Low Gaussian Bypass Select. When GAUSS_BYP is LOW, the gaussian filter is enabled. When GAUSS_BYP is HIGH, the gaussian filter is bypassed. DCVBS Clock Select. When SEL_CLK is LOW, the DCVBS output is clocked at the PXCK. When SEL_CLK is HIGH, the DCVBS output is clocked at the PCK. COMP2DB Offset Selection. When C2DB_OFF is HIGH an offset of 256 is added to the COMP2 output allowing the chrominance data that extends below the sync level to be passed through the outputs. Program Low
3F 3F
6 5
RESERVED GAUSS_BYP
3F
4
SEL_CLK
3F
3
C2DB_OFF
3F
2-0
RESERVED
Subcarrier Register (0x40) 7 6 5 4 FREQL Reg 40 Bit 7-0 Name FREQL Description Subcarrier Frequency. Bits 7-0 of the subcarrier frequency FREQL[31:0]. 3 2 1 0
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PRODUCT SPECIFICATION
TMC2192
Control Register Definitions (continued)
Subcarrier Register (0x41) 7 6 5 4 FREQ3 Reg 41 Bit 7-0 Name FREQ3 Description Subcarrier Frequency. Bits 15-8 of the subcarrier frequency FREQL[31:0]. 3 2 1 0
Subcarrier Register (0x42) 7 6 5 4 FREQ2 Reg 42 Bit 7-0 Name FREQ2 Description Subcarrier Frequency. Bits 23-16 of the subcarrier frequency FREQL[31:0]. 3 2 1 0
Subcarrier Register (0x43) 7 6 5 4 FREQM Reg 43 Bit 7-0 Name FREQM Description Subcarrier Frequency. Bits 31-24 of the subcarrier frequency FREQL[31:0]. 3 2 1 0
Subcarrier Register (0x44) 7 6 5 4 SYSPHL Reg 44 Bit 7-0 Name SYSPHL Description System Phase. Bits 7-0 of the video phase offset SYSPH[15:0]. 3 2 1 0
Subcarrier Register (0x45) 7 6 5 4 SYSPHM Reg 45 Bit 7-0 Name SYSPHM Description System Phase. Bits 15-8 of the video phase offset SYSPH[15:0]. 3 2 1 0
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TMC2192
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Subcarrier Register (0x46) 7 6 5 4 BURPHL Reg 46 Bit 7-0 Name BURPHL Description Burst Phase. Bits 7-0 of the burst phase offset BURPH[15:0]. 3 2 1 0
Subcarrier Register (0x47) 7 6 5 4 BURPHM Reg 47 Bit 7-0 Name BURPHM Description Burst Phase. Bits 15-8 of the burst phase offset BURPH[15:0]. 3 2 1 0
Burst Height Register (0x48) 7 6 5 4 BRSTFULL Reg 48 Bit 7-0 Name BRSTFULL Description Burst Height - Maximum Amplitude. The 8 bit value assigned to U burst component in NTSC and to the U and V components in PAL for the maximum burst amplitude. The burst envelopes midpoint is derived from BRSTFULL. The value programmed into BRSTFULL needs to be .707 of the magnitude of the burst vector. 3 2 1 0
Burst Height Register (0x49) 7 6 5 4 BRST1 Reg 49 Bit 7-0 Name BRST1 Description Burst Height - 1st Intermediate Value. The 8 bit value assigned to U burst component in NTSC and to the U and V components in PAL for the first intermediate value of the burst envelope. The value programmed into BRST1 needs to be .707 of the magnitude of the burst vector. 3 2 1 0
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PRODUCT SPECIFICATION
TMC2192
Control Register Definitions (continued)
Subcarrier Register (0x4A) 7 6 5 4 BRST2 Reg 4A Bit 7-0 Name BRST2 Description Burst Height - 2nd Intermediate Value. The 8 bit value assigned to U burst component in NTSC and to the U and V components in PAL for the second intermediate value of the burst envelope. The value programmed into BRST2 needs to be .707 of the magnitude of the burst vector. 3 2 1 0
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TMC2192
PRODUCT SPECIFICATION
Absolute Maximum Ratings (beyond which the device may be damaged)
Parameter Power Supply Voltage Digital Inputs Applied Voltage2 Forced Current Digital Outputs Applied Voltage2 Forced Current3,4 Short Circuit Duration (Single Output in HIGH state to GND) Analog Output Short Circuit Duration (Single output to GND) Temperature Operating, Ambient Operating, Junction, Plastic package Lead, Soldering (10 seconds) Vapor Phase Soldering (1 minute) Storage -65 -20 +110 +150 +300 +220 +150 C C C C C -0.5 -20.0 VDD + 0.5 20.0 1 Infinite V mA second
3,4
Min. -0.5 -0.5 -20.0
Max. 7.0 VDD + 0.5 20.0
Unit V V mA
Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. 2. Applied voltage must be current limited to specified range, and measured with respect to GND. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current, flowing into the device.
Operating Conditions
Parameter VDD VIH VIL IOH IOL VREF IREF RREF ROUT TA fPXL fPXCK tPWHPX tPWLPX Power Supply Voltage Input Voltage, Logic HIGH Input Voltage, Logic LOW Output Current, Logic HIGH Output Current, Logic LOW External Reference Voltage D/A Converter Reference Current (IREF = VREF / RREF, flowing out of the RREF pin) Reference Resistor, VREF = Nom. Total Output Load Resistance Ambient Temperature, Still Air Pixel Rate Master Clock Rate, 2x pixel rate PXCK Pulse Width, HIGH PXCK Pulse Width, LOW 0 10 20 15 17.5 1.235 1.020 1210 37.5 70 15 30 TTL Compatible Inputs CMOS Compatible Inputs TTL Compatible Inputs CMOS Compatible Inputs Min. 4.75 2.0 0.7VDD GND GND Nom. 5.0 Max. 5.25 VDD VDD 0.8 0.3VDD -2.0 4.0 Units V V V V V mA mA V mA C Mpps MHz ns ns
Pixel Interface
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PRODUCT SPECIFICATION
TMC2192
Operating Conditions (continued)
Parameter tSP tHP tPWLCS tPWHCS tSA tHA tSD tHD tSR tHR tDAL tDAH tSTAH tSTASU tSTOSU tBUFF tDSU tDHO Setup Time Hold Time CS Pulse Width, LOW CS Pulse Width, HIGH Address Setup Time Address Hold Time Data Setup Time (write) Data Hold Time (write) RESET Setup Time RESET Hold Time SCL Pulse Width, LOW SCL Pulse Width, HIGH SDA Start Hold Time SCL to SDA Setup Time (Stop) SCL to SDA Setup Time (Start) SDA Stop Hold Time Setup SDA to SCL Data Setup Time SDA to SCL Data Hold Time Min. 16 0 4 6 17 0 16 0 12 2 1.3 0.6 0.6 0.6 0.6 1.3 300 300 Nom. Max. Units ns ns PXCK PXCK ns ns ns ns ns ns s s s s s s ns ns
Parallel Microprocessor Interface
Serial Interface
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TMC2192
PRODUCT SPECIFICATION
Electrical Characteristics
Symbol IDD IDDQ VRO IBR IIH IIL VOH VOL IOZH IOZL CI CO VOC ROUT COUT Parameter Power Supply Current Power Supply Current (D/A disabled) Voltage Reference Output Input Bias Current, VREF Input Current, Logic HIGH Input Current, Logic LOW Output Voltage, Logic HIGH Output Voltage, Logic LOW Hi-Z Leakage current, HIGH Hi-Z Leakage current, LOW Digital Input Capacitance Digital Output Capacitance Video Output Compliance Voltage Video Output Resistance Video Output Capacitance IOUT = 0 mA, f = 1 MHz VREF = Nom. VDD = Max., VIN = VDD VDD = Max., VIN = GND IOH = Max. IOL = Max. VDD = Max., VIN = VDD VDD = Max., VIN = GND TA = 25C, f = 1MHz TA = 25C, f = 1MHz -0.3 15 15 25 4 10 2.0 2.4 0.4 10 -10 10 Conditions VDD = Max., fPXCK = 27MHz VDD = Max., fPXCK = 27MHz Min. Typ. 335 15 1.235 50 10 -10 Max. 375 25 Units mA mA V A A A V V A A pF pF V k pF
Notes: 1. Typical IDD with VDD = +5.0 Volts and TA = 25C. 2. Timing reference points are at the 50% level.
Switching Characteristics
Parameter PIPES tDOZ tDOM tHOM tDO tR tF tDOV Pipeline Delay Output Delay, CS to low-Z Output Delay, CS to Data Valid Output Hold Time, CS to hi-Z Output Delay D/A Output Current Risetime D/A Output Current Falltime Analog Output Delay PXCK to HSOUT, VSOUT, PDC, LINE, FLD 10% to 90% of full-scale 90% to 10% of full-scale 2 2 10 10 15 Conditions PD to Analog Out PD to DCVBS 4 Min. Typ. Max. 64 66 15 15 Units PXCK Periods ns ns ns ns ns ns ns
Notes: 1. Timing reference points are at the 50% level. 2. Analog CLOAD <10 pF, D7-0 load <40 pF. 3. Pipeline delay, with respect to PXCK, is a function of the phase relationship between the internally generated PCK (PXCK/2) and PXCK, as established by the hardware RESET.
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PRODUCT SPECIFICATION
TMC2192
System Performance Characteristics
Parameter RES ELI ELD EG dp dg SKEW PSRR D/A Converter Resolution Integral Linearity Error Differential Linearity Error (monotonic) Gain Error Differential Phase Differential Gain CHROMA to LUMA Output Skew Power Supply Rejection Ratio f=1kHz PXCK = 27.00 MHz,40 IRE Ramp PXCK = 27.00 MHz,40 IRE Ramp 0.5 0.9 0 0.5 1 Conditions Min. 10 Typ. 10 Max. 10 0.25 0.10 7.5 Units Bits % % %FS degree % ns %/%VDD
Notes: 1. TTL input levels are 0.0 and 3.0 Volts, 10%-90% rise and fall times <3 ns. 2. Analog CLOAD <10 pF, D7-0 load <40 pF.
Applications Discussion
The suggested output reconstruction filter is shown in Figure 29. The phase and frequency response for the encoder and the reconstruction filter is shown in Figure 30.
C6 27pF
The circuit in Figure 31 shows the connection of power supply voltages, output reconstruction filters and the external voltage reference. All VDD pins should be connected to the same power source. The full-scale output voltage level for each D/A:
L5 1.8H A_IN R8 75 C7 330pF C7 330pF
D1 DIODE SCHOTTKY A_OUT D2 DIODE SCHOTTKY
VOUTx = IOUTx x RLx = K x IREFx x RLx = K x (VREF/RREFx) x RLx where: * IOUTx is the full-scale output current sourced by the D/A converter. * RLx is the resistive load on the D/A output pin.
C8 100pF
R9 75
L6 1.0H
65-6294-31
* K is a constant for the TMC2192 D/A converters (approximately equal to 34). * IREFx is the reference current flowing out of the RREFx pin to ground. * VREF is the voltage measured on the VREF pin. * RREFx is the total resistance connected between the RREFx pin and ground. The reference voltage in Figure 31 is from an LM185 1.2 Volt band-gap reference. The suggested trim is designed to give 10% of trim around 5K Ohms. This RREFx sets the "gain" for that D/A converter. Varying RREFx 10% will cause the full-scale output voltage on the D/A to vary by 10%. An alternative output reconstruction filter is the Microelectronic Modules Corp. ST-163E, which contains 4 independent reconstruction filter. The phase and frequency response of this filter is shown in the Output Low-Pass Filters Section of this data sheet. 63
Figure 28. Typical Analog Reconstruction Filter
0 Attenuation (dB)
0
-10
90
Phase (deg)
-20
180
-30
270
-40 0 5 10 15 20 25 Frequency (MHz)
360
65-6294-32
Figure 29. Overall Response
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TMC2192
PRODUCT SPECIFICATION
Layout Considerations
Designing with high-performance mixed-signal circuits demands printed circuits with ground planes. Wire-wrap is not an option. Overall system performance is strongly influenced by the board layout. Capacitive coupling from digital to analog circuits may result in poor picture quality. Consider the following suggestions when doing the layout: * Keep analog traces (CBYPx, VREF, RREF, DACx) as short and far from all digital signals as possible. The TMC2192 should be located near the board edge, close to the analog output connectors. The power plane for the TMC2192 should be separate from that which supplies other digital circuitry. A single power plane should be used for all of the VDD pins. If the power supply for the TMC2192 is the same for the system's digital circuitry, power to the TMC2192 should be filtered with ferrite beads and 0.1F capacitors to reduce noise. The ground plane should be solid, not cross-hatched. Connections to the ground plane should be very short.
*
Decoupling capacitors should be applied liberally to pins. For best results, use 0.1F capacitors. Lead lengths should be minimized. Ceramic chip capacitors are the best choice. If there is dedicated digital power plane, it should not overlap the TMC2192 footprint, the voltage reference, or the analog outputs. Capacitive coupling of digital power supply noise from this layer to the TMC2192 and its related analog circuitry can have an adverse effect on performance. The PXCK should be handled carefully. Jitter and noise on this clock or its ground reference will translate to noise on the video outputs. Terminate the clock line carefully to eliminate overshoot and ringing. Connect all unused inputs to the TMC2192 to either ground or VDD. Do not leave them unconnected.
*
*
*
*
*
64
REV. 1.0.0 8/13/03
39 54 72 96
PRODUCT SPECIFICATION
AGND
VDD VDD VDD VDD
19 A_IN TP18 DA1 ST-163E AIN TP20 DA2 DIN TP22 DA3 BIN TP24 DA4 CIN {Schematic} COUT TP25 ODA4 BOUT TP23 ODA3 DOUT TP21 ODA2 AOUT 1
2
TP16 LPF RDA {Schematic} A_OUT TP19 ODA1 J3 DAC1 1
2 2
2
COMP
2
1
2
1
C55 0.1uF
C56 0.1uF
C57 0.1uF
C58 0.1uF
R33 8.25K Ohm
R37 10K Pot 2
R35 8.25K Ohm
1 3
TP26 PXCK TP28 HSOUT R40 4K7 80 79 78 77 76 83 82 81 FLD0 FLD1 FLD2 TP29 HSIN TP30 VSIN
TP27 VSOUT
1
HSIN VSIN HSOUT VSOUT EMCU1 EDCVBSEN\ HSIN VSIN PDC HSOUT VSOUT
R36 10K Pot 2
1
3
SCL SDA ESA1 ESA0
DGND DGND DGND DGND DGND
SCL SDA EMCU2 EMCU3
57 58 59 60 61 62 DCVEN SER CS/SCL R/W/SDA A1/SA1 A0/SA0
26 40 53 71 97
D0 D1 D2 D3 D4 D5 D6 D7
4 9 AGND 14 AGND 100 AGND AGND
70 69 68 67 66 65 64 63
DCVBS0 DCVBS1 DCVBS2 DCVBS3 DCVBS4 DCVBS5 DCVBS6 DCVBS7 DCVBS8 DCVBS9
R27 TMC2192KJC VDD DCVBS[0..9] DCVBS[0..9] C54 0.1uF
2 1
EMCU[0..3]
EMCU[0..3]
3.3K Ohm D4 1.235V
VCC
C61 0.1uF
C62 0.1uF
C63 0.1uF
C64 0.1uF
C65 0.1uF
C66 0.1uF
C67 0.1uF
C68 0.1uF
HSOUT VSOUT
STUFF EITHER C54 OR D4
3
Figure 30. Typical Layout
ECVBS0 ECVBS1 ECVBS2 ECVBS3 ECVBS4 ECVBS5 ECVBS6 ECVBS7 ECVBS8 ECVBS9 VDDA VDDA VDDA VDDA 93 92 91 90 89 88 87 86 85 84 CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 CVBS5 CVBS6 CVBS7 CVBS8 CVBS9 PXCK RESET LINE0 LINE1 LINE2 LINE3 LINE4 ERESET\ 95 94 EMCU0
VDD JP13 R28 10K Ohm R30 10K Ohm
EPXCK
R32 8.25K Ohm
R34 8.25K Ohm
R38 10K Pot 2
56 55 73 74 75
1 2 3 4 5 6 7 8
3
REV. 1.0.0 8/13/03
VCC U? TP17 ORDA 1 J2 RDAC AGND 15 LUMA 10 J4 DAC2 1 J5 DAC3 J6 DAC4 CHROMA 5 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 52 51 50 49 48 47 46 45 44 43 42 41 38 37 36 35 34 33 32 31 30 29 28 27 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 R_COMP R_CHROMA R_LUMA AGND V_REF OL0 OL1 OL2 OL3 OL4 KEY C_COMP C_CHROMA C_LUMA VDDA 3 6 11 16 98 CONNECT Cx TO VDDA PIN AND CBYPy PIN DIRECTLY R29 10K Ohm R31 10K Ohm 99 8 13 18 25 24 23 22 21 20 OLENG0 OLENG1 OLENG2 OLENG3 OLENG4 OLENG5 R39 10K Pot 2 VDD 1 7 12 17
PD[0..23]
PD[0..23]
OLENGI[0..5]
OLENG[0..5]
ECVBS[0..9]
ECVBS[0..9]
TMC2192
65
66
VCC R57 10K U9 1 AIN DIN CIN BIN BOUT 8 COUT 17 DOUT 20 AOUT 24 13 12 JP14 A2XEN R42 D JUMPER JP15 B2XEN JUMPER JP16 C2XEN JUMPER JP17 D2XEN R45 75 R46 75 R47 75 R48 75 JUMPER JP18 NC1EN JUMPER JP19 NC2EN JUMPER DO NOT STUFF Title ST-163E Size A Date: Document Number TMB2192 Thursday, September 04, 1997 Sheet 7 of 12
65-6294-34
TMC2192
R58 10K
R59 10K
R60 10K
R61 10K
R62 10K
AIN
5
AOUT DOUT COUT BOUT
DIN
CIN
BIN R43 D R44 D 4 9 16 21 A2X B2X C2X D2X NC1 NC2 ST-163E 7 18
R41 D
D IS150 OHM (1%)
Figure 31. ST-163E Layout
JP20 JUMPER
JP21 JUMPER
JP22 JUMPER
JP23 JUMPER
ALL 1%
PRODUCT SPECIFICATION
Rev 0.9.0
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PRODUCT SPECIFICATION
TMC2192
Output Low-Pass Filters
The response at 5.0MHz typically varies < 0.25dB with supplies of 5V to 8V. When operating in the 0dB gain
mode, pin 6 must be well isolated from ground planes. When operating in the +6dB gain mode, pin 6 must have a low resistance path to ground.
Figure 32. Pass Band
Figure 33. Stop Band
Figure 34. 2T Pulse
Figure 35. Group Delay
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TMC2192
PRODUCT SPECIFICATION
Mechanical Dimensions
100-Lead MQFP
Inches Min. A A1 A2 B C D D1 E E1 e L N ND NE
ccc
Symbol
Millimeters Min. Max.
Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Controlling dimension is millimeters. 3. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot. 4. "L" is the length of terminal for soldering to a substrate. 5. "B" & "C" includes lead finish thickness.
Max.
-- .134 .010 -- .100 .120 .015 .008 .009 .005 .904 .923 .783 .791 .667 .687 .547 .555 .0256 BSC .028 .040 100 30 20 0 -- 7 .004
-- 3.40 .25 -- 2.55 3.05 .38 .22 .23 .13 22.95 23.45 19.90 20.10 16.95 17.45 13.90 14.10 .65 BSC .73 1.03 100 30 20 0 -- 7 .12
3, 5 5
4
D D1 Datum Plane B Pin 1 Indentifier E e 0.076" (1.95mm) Ref Lead Detail E1 .13 (.005) R Min. L .20 (.008) Min. 0 Min. .13 (.30) R .005 (.012) C
See Lead Detail A A2 B A1 Seating Plane Base Plane -CLead Coplanarity ccc C
68
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TMC2192
PRODUCT SPECIFICATION
Ordering Information
Product Number TMC2192KHC Temperature Range TA = 0C to 70C Screening Commercial Package 100-pin MQFP Package Marking TMC2192KHC
Life Support Policy
8/13/03 0.0m 002 Stock#DS30002192

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